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58 #ifndef __ARCH_X86_MISCREGS_HH__
59 #define __ARCH_X86_MISCREGS_HH__
61 #include "arch/x86/x86_traits.hh"
62 #include "base/bitunion.hh"
64 //These get defined in some system headers (at least termbits.h). That confuses
65 //things here significantly.
87 // Most of these are invalid.
89 MISCREG_CR0 = MISCREG_CR_BASE,
107 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
108 MISCREG_DR0 = MISCREG_DR_BASE,
118 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
121 * Model Specific Registers
123 // Time stamp counter
129 MISCREG_SYSENTER_ESP,
130 MISCREG_SYSENTER_EIP,
136 MISCREG_DEBUG_CTL_MSR,
138 MISCREG_LAST_BRANCH_FROM_IP,
139 MISCREG_LAST_BRANCH_TO_IP,
140 MISCREG_LAST_EXCEPTION_FROM_IP,
141 MISCREG_LAST_EXCEPTION_TO_IP,
143 MISCREG_MTRR_PHYS_BASE_BASE,
144 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
145 MISCREG_MTRR_PHYS_BASE_1,
146 MISCREG_MTRR_PHYS_BASE_2,
147 MISCREG_MTRR_PHYS_BASE_3,
148 MISCREG_MTRR_PHYS_BASE_4,
149 MISCREG_MTRR_PHYS_BASE_5,
150 MISCREG_MTRR_PHYS_BASE_6,
151 MISCREG_MTRR_PHYS_BASE_7,
153 MISCREG_MTRR_PHYS_MASK_BASE,
154 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
155 MISCREG_MTRR_PHYS_MASK_1,
156 MISCREG_MTRR_PHYS_MASK_2,
157 MISCREG_MTRR_PHYS_MASK_3,
158 MISCREG_MTRR_PHYS_MASK_4,
159 MISCREG_MTRR_PHYS_MASK_5,
160 MISCREG_MTRR_PHYS_MASK_6,
161 MISCREG_MTRR_PHYS_MASK_7,
163 MISCREG_MTRR_FIX_64K_00000,
164 MISCREG_MTRR_FIX_16K_80000,
165 MISCREG_MTRR_FIX_16K_A0000,
166 MISCREG_MTRR_FIX_4K_C0000,
167 MISCREG_MTRR_FIX_4K_C8000,
168 MISCREG_MTRR_FIX_4K_D0000,
169 MISCREG_MTRR_FIX_4K_D8000,
170 MISCREG_MTRR_FIX_4K_E0000,
171 MISCREG_MTRR_FIX_4K_E8000,
172 MISCREG_MTRR_FIX_4K_F0000,
173 MISCREG_MTRR_FIX_4K_F8000,
180 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
186 MISCREG_MC_STATUS_BASE,
187 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
193 MISCREG_MC_ADDR_BASE,
194 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
200 MISCREG_MC_MISC_BASE,
201 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
207 // Extended feature enable register
216 MISCREG_KERNEL_GS_BASE,
220 MISCREG_PERF_EVT_SEL_BASE,
221 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
222 MISCREG_PERF_EVT_SEL1,
223 MISCREG_PERF_EVT_SEL2,
224 MISCREG_PERF_EVT_SEL3,
226 MISCREG_PERF_EVT_CTR_BASE,
227 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
228 MISCREG_PERF_EVT_CTR1,
229 MISCREG_PERF_EVT_CTR2,
230 MISCREG_PERF_EVT_CTR3,
234 MISCREG_IORR_BASE_BASE,
235 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
238 MISCREG_IORR_MASK_BASE,
239 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
254 MISCREG_SEG_SEL_BASE,
255 MISCREG_ES = MISCREG_SEG_SEL_BASE,
261 MISCREG_INT, // This isn't actually used.
263 // Hidden segment base field
264 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
265 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
273 // The effective segment base, ie what is actually added to an
274 // address. In 64 bit mode this can be different from the above,
276 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
277 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
283 MISCREG_INT_EFF_BASE,
285 // Hidden segment limit field
286 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NumSegments,
287 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
293 MISCREG_INT_LIMIT, // This isn't actually used.
295 // Hidden segment limit attributes
296 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
297 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
303 MISCREG_INT_ATTR, // This isn't actually used.
305 // System segment selectors
306 MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
307 MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
310 // Hidden system segment base field
311 MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
312 MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
317 // Hidden system segment limit field
318 MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
319 MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
324 // Hidden system segment attribute field
325 MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
326 MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
329 // Floating point control registers
330 MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments,
332 //XXX Add "Model-Specific Registers"
337 static inline MiscRegIndex
338 MISCREG_CR(int index)
340 return (MiscRegIndex)(MISCREG_CR_BASE + index);
343 static inline MiscRegIndex
344 MISCREG_DR(int index)
346 return (MiscRegIndex)(MISCREG_DR_BASE + index);
349 static inline MiscRegIndex
350 MISCREG_MTRR_PHYS_BASE(int index)
352 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
355 static inline MiscRegIndex
356 MISCREG_MTRR_PHYS_MASK(int index)
358 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
361 static inline MiscRegIndex
362 MISCREG_MC_CTL(int index)
364 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
367 static inline MiscRegIndex
368 MISCREG_MC_STATUS(int index)
370 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
373 static inline MiscRegIndex
374 MISCREG_MC_ADDR(int index)
376 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
379 static inline MiscRegIndex
380 MISCREG_MC_MISC(int index)
382 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
385 static inline MiscRegIndex
386 MISCREG_PERF_EVT_SEL(int index)
388 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
391 static inline MiscRegIndex
392 MISCREG_PERF_EVT_CTR(int index)
394 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
397 static inline MiscRegIndex
398 MISCREG_IORR_BASE(int index)
400 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
403 static inline MiscRegIndex
404 MISCREG_IORR_MASK(int index)
406 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
409 static inline MiscRegIndex
410 MISCREG_SEG_SEL(int index)
412 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
415 static inline MiscRegIndex
416 MISCREG_SEG_BASE(int index)
418 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
421 static inline MiscRegIndex
422 MISCREG_SEG_EFF_BASE(int index)
424 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
427 static inline MiscRegIndex
428 MISCREG_SEG_LIMIT(int index)
430 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
433 static inline MiscRegIndex
434 MISCREG_SEG_ATTR(int index)
436 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
439 static inline MiscRegIndex
440 MISCREG_SYSSEG_SEL(int index)
442 return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
445 static inline MiscRegIndex
446 MISCREG_SYSSEG_BASE(int index)
448 return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
451 static inline MiscRegIndex
452 MISCREG_SYSSEG_LIMIT(int index)
454 return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
457 static inline MiscRegIndex
458 MISCREG_SYSSEG_ATTR(int index)
460 return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
464 * A type to describe the condition code bits of the RFLAGS register,
465 * plus two flags, EZF and ECF, which are only visible to microcode.
467 BitUnion64(CCFlagBits)
476 EndBitUnion(CCFlagBits)
482 Bitfield<21> id; // ID Flag
483 Bitfield<20> vip; // Virtual Interrupt Pending
484 Bitfield<19> vif; // Virtual Interrupt Flag
485 Bitfield<18> ac; // Alignment Check
486 Bitfield<17> vm; // Virtual-8086 Mode
487 Bitfield<16> rf; // Resume Flag
488 Bitfield<14> nt; // Nested Task
489 Bitfield<13, 12> iopl; // I/O Privilege Level
490 Bitfield<11> of; // Overflow Flag
491 Bitfield<10> df; // Direction Flag
492 Bitfield<9> intf; // Interrupt Flag
493 Bitfield<8> tf; // Trap Flag
494 Bitfield<7> sf; // Sign Flag
495 Bitfield<6> zf; // Zero Flag
496 Bitfield<4> af; // Auxiliary Flag
497 Bitfield<2> pf; // Parity Flag
498 Bitfield<0> cf; // Carry Flag
505 Bitfield<31> pg; // Paging
506 Bitfield<30> cd; // Cache Disable
507 Bitfield<29> nw; // Not Writethrough
508 Bitfield<18> am; // Alignment Mask
509 Bitfield<16> wp; // Write Protect
510 Bitfield<5> ne; // Numeric Error
511 Bitfield<4> et; // Extension Type
512 Bitfield<3> ts; // Task Switched
513 Bitfield<2> em; // Emulation
514 Bitfield<1> mp; // Monitor Coprocessor
515 Bitfield<0> pe; // Protection Enabled
518 // Page Fault Virtual Address
520 Bitfield<31, 0> legacy;
524 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
526 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
528 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
530 Bitfield<4> pcd; // Page-Level Cache Disable
531 Bitfield<3> pwt; // Page-Level Writethrough
535 Bitfield<10> osxmmexcpt; // Operating System Unmasked
537 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
538 Bitfield<8> pce; // Performance-Monitoring Counter Enable
539 Bitfield<7> pge; // Page-Global Enable
540 Bitfield<6> mce; // Machine Check Enable
541 Bitfield<5> pae; // Physical-Address Extension
542 Bitfield<4> pse; // Page Size Extensions
543 Bitfield<3> de; // Debugging Extensions
544 Bitfield<2> tsd; // Time Stamp Disable
545 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
546 Bitfield<0> vme; // Virtual-8086 Mode Extensions
550 Bitfield<3, 0> tpr; // Task Priority Register
555 Bitfield<7, 0> vcnt; // Variable-Range Register Count
556 Bitfield<8> fix; // Fixed-Range Registers
557 Bitfield<10> wc; // Write-Combining
561 * SYSENTER configuration registers
563 BitUnion64(SysenterCS)
564 Bitfield<15, 0> targetCS;
565 EndBitUnion(SysenterCS)
567 BitUnion64(SysenterESP)
568 Bitfield<31, 0> targetESP;
569 EndBitUnion(SysenterESP)
571 BitUnion64(SysenterEIP)
572 Bitfield<31, 0> targetEIP;
573 EndBitUnion(SysenterEIP)
576 * Global machine check registers
579 Bitfield<7, 0> count; // Number of error reporting register banks
580 Bitfield<8> MCGCP; // MCG_CTL register present.
583 BitUnion64(McgStatus)
584 Bitfield<0> ripv; // Restart-IP valid
585 Bitfield<1> eipv; // Error-IP valid
586 Bitfield<2> mcip; // Machine check in-progress
587 EndBitUnion(McgStatus)
589 BitUnion64(DebugCtlMsr)
590 Bitfield<0> lbr; // Last-branch record
591 Bitfield<1> btf; // Branch single step
592 Bitfield<2> pb0; // Performance monitoring pin control 0
593 Bitfield<3> pb1; // Performance monitoring pin control 1
594 Bitfield<4> pb2; // Performance monitoring pin control 2
595 Bitfield<5> pb3; // Performance monitoring pin control 3
596 /*uint64_t pb(int index)
598 return bits(__data, index + 2);
600 EndBitUnion(DebugCtlMsr)
602 BitUnion64(MtrrPhysBase)
603 Bitfield<7, 0> type; // Default memory type
604 Bitfield<51, 12> physbase; // Range physical base address
605 EndBitUnion(MtrrPhysBase)
607 BitUnion64(MtrrPhysMask)
608 Bitfield<11> valid; // MTRR pair enable
609 Bitfield<51, 12> physmask; // Range physical mask
610 EndBitUnion(MtrrPhysMask)
612 BitUnion64(MtrrFixed)
613 /*uint64_t type(int index)
615 return bits(__data, index * 8 + 7, index * 8);
617 EndBitUnion(MtrrFixed)
620 /*uint64_t pa(int index)
622 return bits(__data, index * 8 + 2, index * 8);
626 BitUnion64(MtrrDefType)
627 Bitfield<7, 0> type; // Default type
628 Bitfield<10> fe; // Fixed range enable
629 Bitfield<11> e; // MTRR enable
630 EndBitUnion(MtrrDefType)
636 Bitfield<15,0> mcaErrorCode;
637 Bitfield<31,16> modelSpecificCode;
638 Bitfield<56,32> otherInfo;
639 Bitfield<57> pcc; // Processor-context corrupt
640 Bitfield<58> addrv; // Error-address register valid
641 Bitfield<59> miscv; // Miscellaneous-error register valid
642 Bitfield<60> en; // Error condition enabled
643 Bitfield<61> uc; // Uncorrected error
644 Bitfield<62> over; // Status register overflow
645 Bitfield<63> val; // Valid
646 EndBitUnion(McStatus)
649 /*uint64_t en(int index)
651 return bits(__data, index);
655 // Extended feature enable register
657 Bitfield<0> sce; // System call extensions
658 Bitfield<8> lme; // Long mode enable
659 Bitfield<10> lma; // Long mode active
660 Bitfield<11> nxe; // No-execute enable
661 Bitfield<12> svme; // Secure virtual machine enable
662 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
666 Bitfield<31,0> targetEip;
667 Bitfield<47,32> syscallCsAndSs;
668 Bitfield<63,48> sysretCsAndSs;
675 BitUnion64(PerfEvtSel)
676 Bitfield<7,0> eventMask;
677 Bitfield<15,8> unitMask;
678 Bitfield<16> usr; // User mode
679 Bitfield<17> os; // Operating-system mode
680 Bitfield<18> e; // Edge detect
681 Bitfield<19> pc; // Pin control
682 Bitfield<20> intEn; // Interrupt enable
683 Bitfield<22> en; // Counter enable
684 Bitfield<23> inv; // Invert mask
685 Bitfield<31,24> counterMask;
686 EndBitUnion(PerfEvtSel)
689 Bitfield<18> mfde; // MtrrFixDramEn
690 Bitfield<19> mfdm; // MtrrFixDramModEn
691 Bitfield<20> mvdm; // MtrrVarDramEn
692 Bitfield<21> tom2; // MtrrTom2En
696 Bitfield<3> wr; // WrMem Enable
697 Bitfield<4> rd; // RdMem Enable
698 Bitfield<51,12> physbase; // Range physical base address
699 EndBitUnion(IorrBase)
702 Bitfield<11> v; // I/O register pair enable (valid)
703 Bitfield<51,12> physmask; // Range physical mask
704 EndBitUnion(IorrMask)
707 Bitfield<51,23> physAddr; // Top of memory physical address
718 EndBitUnion(IgnneMsr)
720 BitUnion64(SmmCtlMsr)
723 Bitfield<2> smiCycle;
725 Bitfield<4> rsmCycle;
726 EndBitUnion(SmmCtlMsr)
731 BitUnion64(SegSelector)
732 Bitfield<15, 3> si; // Selector Index
733 Bitfield<2> ti; // Table Indicator
734 Bitfield<1, 0> rpl; // Requestor Privilege Level
735 EndBitUnion(SegSelector)
738 * Segment Descriptors
741 BitUnion64(SegDescriptor)
742 Bitfield<63, 56> baseHigh;
743 Bitfield<39, 16> baseLow;
744 Bitfield<55> g; // Granularity
745 Bitfield<54> d; // Default Operand Size
746 Bitfield<54> b; // Default Operand Size
747 Bitfield<53> l; // Long Attribute Bit
748 Bitfield<52> avl; // Available To Software
749 Bitfield<51, 48> limitHigh;
750 Bitfield<15, 0> limitLow;
751 Bitfield<47> p; // Present
752 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
753 Bitfield<44> s; // System
754 SubBitUnion(type, 43, 40)
755 // Specifies whether this descriptor is for code or data.
756 Bitfield<43> codeOrData;
758 // These bit fields are for code segments
759 Bitfield<42> c; // Conforming
760 Bitfield<41> r; // Readable
762 // These bit fields are for data segments
763 Bitfield<42> e; // Expand-Down
764 Bitfield<41> w; // Writable
766 // This is used for both code and data segments.
767 Bitfield<40> a; // Accessed
769 EndBitUnion(SegDescriptor)
772 Bitfield<0> writable;
773 Bitfield<1> readable;
774 Bitfield<2> expandDown;
776 Bitfield<5> defaultSize;
777 Bitfield<6> longMode;
780 BitUnion64(GateDescriptor)
781 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
782 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
783 Bitfield<31, 16> selector; // Target Code-Segment Selector
784 Bitfield<47> p; // Present
785 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
786 Bitfield<43, 40> type;
787 Bitfield<36, 32> count; // Parameter Count
788 EndBitUnion(GateDescriptor)
791 * Descriptor-Table Registers
809 #endif // __ARCH_X86_INTREGS_HH__