src/arch/x86/miscregs.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
   7  * following conditions are met:
   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
  11  * compensation for, or commercial advantage from such use.  Illustrative
  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
  14  * Illustrative examples of commercial use are distributing products for
  15  * commercial advantage and providing services using the software for
  16  * commercial advantage.
  17  *
  18  * If you wish to use this software or functionality therein that may be
  19  * covered by patents for commercial use, please contact:
  20  *     Director of Intellectual Property Licensing
  21  *     Office of Strategy and Technology
  22  *     Hewlett-Packard Company
  23  *     1501 Page Mill Road
  24  *     Palo Alto, California  94304
  25  *
  26  * Redistributions of source code must retain the above copyright notice,
  27  * this list of conditions and the following disclaimer.  Redistributions
  28  * in binary form must reproduce the above copyright notice, this list of
  29  * conditions and the following disclaimer in the documentation and/or
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  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  32  * contributors may be used to endorse or promote products derived from
  33  * this software without specific prior written permission.  No right of
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  35  * output created using the software may be prepared, but only for
  36  * Non-Commercial Uses.  Derivatives of the software may be shared with
  37  * others provided: (i) the others agree to abide by the list of
  38  * conditions herein which includes the Non-Commercial Use restrictions;
  39  * and (ii) such Derivatives of the software include the above copyright
  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_MISCREGS_HH__
  59 #define __ARCH_X86_MISCREGS_HH__
  60
  61 #include "base/bitunion.hh"
  62
  63 namespace X86ISA
  64 {
  65     enum CondFlagBit {
  66         CFBit = 1 << 0,
  67         PFBit = 1 << 2,
  68         ECFBit = 1 << 3,
  69         AFBit = 1 << 4,
  70         EZFBit = 1 << 5,
  71         ZFBit = 1 << 6,
  72         SFBit = 1 << 7,
  73         DFBit = 1 << 10,
  74         OFBit = 1 << 11
  75     };
  76
  77     enum MiscRegIndex
  78     {
  79         // Control registers
  80         // Most of these are invalid.
  81         MISCREG_CR_BASE,
  82         MISCREG_CR0 = MISCREG_CR_BASE,
  83         MISCREG_CR1,
  84         MISCREG_CR2,
  85         MISCREG_CR3,
  86         MISCREG_CR4,
  87         MISCREG_CR5,
  88         MISCREG_CR6,
  89         MISCREG_CR7,
  90         MISCREG_CR8,
  91         MISCREG_CR9,
  92         MISCREG_CR10,
  93         MISCREG_CR11,
  94         MISCREG_CR12,
  95         MISCREG_CR13,
  96         MISCREG_CR14,
  97         MISCREG_CR15,
  98
  99         // Debug registers
 100         MISCREG_DR_BASE,
 101         MISCREG_DR0 = MISCREG_DR_BASE,
 102         MISCREG_DR1,
 103         MISCREG_DR2,
 104         MISCREG_DR3,
 105         MISCREG_DR4,
 106         MISCREG_DR5,
 107         MISCREG_DR6,
 108         MISCREG_DR7,
 109
 110         // Flags register
 111         MISCREG_RFLAGS,
 112
 113         // Segment selectors
 114         MISCREG_SEG_SEL_BASE,
 115         MISCREG_ES = MISCREG_SEG_SEL_BASE,
 116         MISCREG_CS,
 117         MISCREG_SS,
 118         MISCREG_DS,
 119         MISCREG_FS,
 120         MISCREG_GS,
 121
 122         // Hidden segment base field
 123         MISCREG_SEG_BASE_BASE,
 124         MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
 125         MISCREG_CS_BASE,
 126         MISCREG_SS_BASE,
 127         MISCREG_DS_BASE,
 128         MISCREG_FS_BASE,
 129         MISCREG_GS_BASE,
 130
 131         // Hidden segment limit field
 132         MISCREG_SEG_LIMIT_BASE,
 133         MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
 134         MISCREG_CS_LIMIT,
 135         MISCREG_SS_LIMIT,
 136         MISCREG_DS_LIMIT,
 137         MISCREG_FS_LIMIT,
 138         MISCREG_GS_LIMIT,
 139
 140         // Hidden segment limit attributes
 141         MISCREG_SEG_ATTR_BASE,
 142         MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
 143         MISCREG_CS_ATTR,
 144         MISCREG_SS_ATTR,
 145         MISCREG_DS_ATTR,
 146         MISCREG_FS_ATTR,
 147         MISCREG_GS_ATTR,
 148
 149         // System segment selectors
 150         MISCREG_SYSSEG_SEL_BASE,
 151         MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
 152         MISCREG_TR,
 153
 154         // Hidden system segment base field
 155         MISCREG_SYSSEG_BASE_BASE,
 156         MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
 157         MISCREG_TR_BASE,
 158         MISCREG_GDTR_BASE,
 159         MISCREG_IDTR_BASE,
 160
 161         // Hidden system segment limit field
 162         MISCREG_SYSSEG_LIMIT_BASE,
 163         MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
 164         MISCREG_TR_LIMIT,
 165         MISCREG_GDTR_LIMIT,
 166         MISCREG_IDTR_LIMIT,
 167
 168         // Hidden system segment attribute field
 169         MISCREG_SYSSEG_ATTR_BASE,
 170         MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
 171         MISCREG_TR_ATTR,
 172
 173         //XXX Add "Model-Specific Registers"
 174
 175         NUM_MISCREGS
 176     };
 177
 178     /**
 179      * A type to describe the condition code bits of the RFLAGS register,
 180      * plus two flags, EZF and ECF, which are only visible to microcode.
 181      */
 182     BitUnion64(CCFlagBits)
 183         Bitfield<11> OF;
 184         Bitfield<7> SF;
 185         Bitfield<6> ZF;
 186         Bitfield<5> EZF;
 187         Bitfield<4> AF;
 188         Bitfield<3> ECF;
 189         Bitfield<2> PF;
 190         Bitfield<0> CF;
 191     EndBitUnion(CCFlagBits)
 192
 193     /**
 194      * RFLAGS
 195      */
 196     BitUnion64(RFLAGS)
 197         Bitfield<21> ID; // ID Flag
 198         Bitfield<20> VIP; // Virtual Interrupt Pending
 199         Bitfield<19> VIF; // Virtual Interrupt Flag
 200         Bitfield<18> AC; // Alignment Check
 201         Bitfield<17> VM; // Virtual-8086 Mode
 202         Bitfield<16> RF; // Resume Flag
 203         Bitfield<14> NT; // Nested Task
 204         Bitfield<13, 12> IOPL; // I/O Privilege Level
 205         Bitfield<11> OF; // Overflow Flag
 206         Bitfield<10> DF; // Direction Flag
 207         Bitfield<9> IF; // Interrupt Flag
 208         Bitfield<8> TF; // Trap Flag
 209         Bitfield<7> SF; // Sign Flag
 210         Bitfield<6> ZF; // Zero Flag
 211         Bitfield<4> AF; // Auxiliary Flag
 212         Bitfield<2> PF; // Parity Flag
 213         Bitfield<0> CF; // Carry Flag
 214     EndBitUnion(RFLAGS)
 215
 216     /**
 217      * Control registers
 218      */
 219     BitUnion64(CR0)
 220         Bitfield<31> PG; // Paging
 221         Bitfield<30> CD; // Cache Disable
 222         Bitfield<29> NW; // Not Writethrough
 223         Bitfield<18> AM; // Alignment Mask
 224         Bitfield<16> WP; // Write Protect
 225         Bitfield<5> NE; // Numeric Error
 226         Bitfield<4> ET; // Extension Type
 227         Bitfield<3> TS; // Task Switched
 228         Bitfield<2> EM; // Emulation
 229         Bitfield<1> MP; // Monitor Coprocessor
 230         Bitfield<0> PE; // Protection Enabled
 231     EndBitUnion(CR0)
 232
 233     // Page Fault Virtual Address
 234     BitUnion64(CR2)
 235         Bitfield<31, 0> legacy;
 236     EndBitUnion(CR2)
 237
 238     BitUnion64(CR3)
 239         Bitfield<51, 12> longPDTB; // Long Mode Page-Directory-Table
 240                                    // Base Address
 241         Bitfield<31, 12> PDTB; // Non-PAE Addressing Page-Directory-Table
 242                                // Base Address
 243         Bitfield<31, 5> PAEPDTB; // PAE Addressing Page-Directory-Table
 244                                  // Base Address
 245         Bitfield<4> PCD; // Page-Level Cache Disable
 246         Bitfield<3> PWT; // Page-Level Writethrough
 247     EndBitUnion(CR3)
 248
 249     BitUnion64(CR4)
 250         Bitfield<10> OSXMMEXCPT; // Operating System Unmasked
 251                                  // Exception Support
 252         Bitfield<9> OSFXSR; // Operating System FXSave/FSRSTOR Support
 253         Bitfield<8> PCE; // Performance-Monitoring Counter Enable
 254         Bitfield<7> PGE; // Page-Global Enable
 255         Bitfield<6> MCE; // Machine Check Enable
 256         Bitfield<5> PAE; // Physical-Address Extension
 257         Bitfield<4> PSE; // Page Size Extensions
 258         Bitfield<3> DE; // Debugging Extensions
 259         Bitfield<2> TSD; // Time Stamp Disable
 260         Bitfield<1> PVI; // Protected-Mode Virtual Interrupts
 261         Bitfield<0> VME; // Virtual-8086 Mode Extensions
 262     EndBitUnion(CR4)
 263
 264     BitUnion64(CR8)
 265         Bitfield<3, 0> TPR; // Task Priority Register
 266     EndBitUnion(CR4)
 267
 268     /**
 269      * Segment Selector
 270      */
 271     BitUnion64(SegSelector)
 272         Bitfield<15, 3> SI; // Selector Index
 273         Bitfield<2> TI; // Table Indicator
 274         Bitfield<1, 0> RPL; // Requestor Privilege Level
 275     EndBitUnion(SegSelector)
 276
 277     /**
 278      * Segment Descriptors
 279      */
 280
 281     BitUnion64(SegDescriptor)
 282         Bitfield<63, 56> baseHigh;
 283         Bitfield<39, 16> baseLow;
 284         Bitfield<55> G; // Granularity
 285         Bitfield<54> D; // Default Operand Size
 286         Bitfield<54> B; // Default Operand Size
 287         Bitfield<53> L; // Long Attribute Bit
 288         Bitfield<52> AVL; // Available To Software
 289         Bitfield<51, 48> limitHigh;
 290         Bitfield<15, 0> limitLow;
 291         Bitfield<47> P; // Present
 292         Bitfield<46, 45> DPL; // Descriptor Privilege-Level
 293         Bitfield<44> S; // System
 294         SubBitUnion(type, 43, 40)
 295             // Specifies whether this descriptor is for code or data.
 296             Bitfield<43> codeOrData;
 297
 298             // These bit fields are for code segments
 299             Bitfield<42> C; // Conforming
 300             Bitfield<41> R; // Readable
 301
 302             // These bit fields are for data segments
 303             Bitfield<42> E; // Expand-Down
 304             Bitfield<41> W; // Writable
 305
 306             // This is used for both code and data segments.
 307             Bitfield<40> A; // Accessed
 308         EndSubBitUnion(type)
 309     EndBitUnion(SegDescriptor)
 310
 311     BitUnion64(GateDescriptor)
 312         Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
 313         Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
 314         Bitfield<31, 16> selector; // Target Code-Segment Selector
 315         Bitfield<47> P; // Present
 316         Bitfield<46, 45> DPL; // Descriptor Privilege-Level
 317         Bitfield<43, 40> type;
 318         Bitfield<36, 32> count; // Parameter Count
 319     EndBitUnion(GateDescriptor)
 320
 321     /**
 322      * Descriptor-Table Registers
 323      */
 324     BitUnion64(GDTR)
 325     EndBitUnion(GDTR)
 326
 327     BitUnion64(IDTR)
 328     EndBitUnion(IDTR)
 329
 330     BitUnion64(LDTR)
 331     EndBitUnion(LDTR)
 332
 333     /**
 334      * Task Register
 335      */
 336     BitUnion64(TR)
 337     EndBitUnion(TR)
 338 };
 339
 340 #endif // __ARCH_X86_INTREGS_HH__