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58 #ifndef __ARCH_X86_MISCREGS_HH__
59 #define __ARCH_X86_MISCREGS_HH__
61 #include "arch/x86/segmentregs.hh"
62 #include "arch/x86/x86_traits.hh"
63 #include "base/bitunion.hh"
65 //These get defined in some system headers (at least termbits.h). That confuses
66 //things here significantly.
100 // Most of these are invalid.
102 MISCREG_CR0 = MISCREG_CR_BASE,
120 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
121 MISCREG_DR0 = MISCREG_DR_BASE,
131 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
133 //Register to keep handy values like the CPU mode in.
137 * Model Specific Registers
139 // Time stamp counter
145 MISCREG_SYSENTER_ESP,
146 MISCREG_SYSENTER_EIP,
152 MISCREG_DEBUG_CTL_MSR,
154 MISCREG_LAST_BRANCH_FROM_IP,
155 MISCREG_LAST_BRANCH_TO_IP,
156 MISCREG_LAST_EXCEPTION_FROM_IP,
157 MISCREG_LAST_EXCEPTION_TO_IP,
159 MISCREG_MTRR_PHYS_BASE_BASE,
160 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
161 MISCREG_MTRR_PHYS_BASE_1,
162 MISCREG_MTRR_PHYS_BASE_2,
163 MISCREG_MTRR_PHYS_BASE_3,
164 MISCREG_MTRR_PHYS_BASE_4,
165 MISCREG_MTRR_PHYS_BASE_5,
166 MISCREG_MTRR_PHYS_BASE_6,
167 MISCREG_MTRR_PHYS_BASE_7,
169 MISCREG_MTRR_PHYS_MASK_BASE,
170 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
171 MISCREG_MTRR_PHYS_MASK_1,
172 MISCREG_MTRR_PHYS_MASK_2,
173 MISCREG_MTRR_PHYS_MASK_3,
174 MISCREG_MTRR_PHYS_MASK_4,
175 MISCREG_MTRR_PHYS_MASK_5,
176 MISCREG_MTRR_PHYS_MASK_6,
177 MISCREG_MTRR_PHYS_MASK_7,
179 MISCREG_MTRR_FIX_64K_00000,
180 MISCREG_MTRR_FIX_16K_80000,
181 MISCREG_MTRR_FIX_16K_A0000,
182 MISCREG_MTRR_FIX_4K_C0000,
183 MISCREG_MTRR_FIX_4K_C8000,
184 MISCREG_MTRR_FIX_4K_D0000,
185 MISCREG_MTRR_FIX_4K_D8000,
186 MISCREG_MTRR_FIX_4K_E0000,
187 MISCREG_MTRR_FIX_4K_E8000,
188 MISCREG_MTRR_FIX_4K_F0000,
189 MISCREG_MTRR_FIX_4K_F8000,
196 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
205 MISCREG_MC_STATUS_BASE,
206 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
215 MISCREG_MC_ADDR_BASE,
216 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
225 MISCREG_MC_MISC_BASE,
226 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
235 // Extended feature enable register
244 MISCREG_KERNEL_GS_BASE,
248 MISCREG_PERF_EVT_SEL_BASE,
249 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
250 MISCREG_PERF_EVT_SEL1,
251 MISCREG_PERF_EVT_SEL2,
252 MISCREG_PERF_EVT_SEL3,
254 MISCREG_PERF_EVT_CTR_BASE,
255 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
256 MISCREG_PERF_EVT_CTR1,
257 MISCREG_PERF_EVT_CTR2,
258 MISCREG_PERF_EVT_CTR3,
262 MISCREG_IORR_BASE_BASE,
263 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
266 MISCREG_IORR_MASK_BASE,
267 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
282 MISCREG_SEG_SEL_BASE,
283 MISCREG_ES = MISCREG_SEG_SEL_BASE,
297 // Hidden segment base field
298 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
299 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
313 // The effective segment base, ie what is actually added to an
314 // address. In 64 bit mode this can be different from the above,
316 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
317 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
324 MISCREG_TSL_EFF_BASE,
325 MISCREG_TSG_EFF_BASE,
329 MISCREG_IDTR_EFF_BASE,
331 // Hidden segment limit field
332 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
333 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
347 // Hidden segment limit attributes
348 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
349 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
363 // Floating point control registers
365 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
367 //XXX Add "Model-Specific Registers"
372 MISCREG_APIC_ID = MISCREG_APIC_START,
373 MISCREG_APIC_VERSION,
374 MISCREG_APIC_TASK_PRIORITY,
375 MISCREG_APIC_ARBITRATION_PRIORITY,
376 MISCREG_APIC_PROCESSOR_PRIORITY,
378 MISCREG_APIC_LOGICAL_DESTINATION,
379 MISCREG_APIC_DESTINATION_FORMAT,
380 MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR,
382 MISCREG_APIC_IN_SERVICE_BASE,
384 MISCREG_APIC_TRIGGER_MODE_BASE = MISCREG_APIC_IN_SERVICE_BASE + 16,
386 MISCREG_APIC_INTERRUPT_REQUEST_BASE =
387 MISCREG_APIC_TRIGGER_MODE_BASE + 16,
389 MISCREG_APIC_ERROR_STATUS = MISCREG_APIC_INTERRUPT_REQUEST_BASE + 16,
390 MISCREG_APIC_INTERRUPT_COMMAND_LOW,
391 MISCREG_APIC_INTERRUPT_COMMAND_HIGH,
392 MISCREG_APIC_LVT_TIMER,
393 MISCREG_APIC_LVT_THERMAL_SENSOR,
394 MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS,
395 MISCREG_APIC_LVT_LINT0,
396 MISCREG_APIC_LVT_LINT1,
397 MISCREG_APIC_LVT_ERROR,
398 MISCREG_APIC_INITIAL_COUNT,
399 MISCREG_APIC_CURRENT_COUNT,
400 MISCREG_APIC_DIVIDE_COUNT,
401 MISCREG_APIC_END = MISCREG_APIC_DIVIDE_COUNT,
403 MISCREG_APIC_INTERNAL_STATE,
405 // "Fake" MSRs for internally implemented devices
406 MISCREG_PCI_CONFIG_ADDRESS,
411 static inline MiscRegIndex
412 MISCREG_CR(int index)
414 return (MiscRegIndex)(MISCREG_CR_BASE + index);
417 static inline MiscRegIndex
418 MISCREG_DR(int index)
420 return (MiscRegIndex)(MISCREG_DR_BASE + index);
423 static inline MiscRegIndex
424 MISCREG_MTRR_PHYS_BASE(int index)
426 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
429 static inline MiscRegIndex
430 MISCREG_MTRR_PHYS_MASK(int index)
432 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
435 static inline MiscRegIndex
436 MISCREG_MC_CTL(int index)
438 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
441 static inline MiscRegIndex
442 MISCREG_MC_STATUS(int index)
444 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
447 static inline MiscRegIndex
448 MISCREG_MC_ADDR(int index)
450 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
453 static inline MiscRegIndex
454 MISCREG_MC_MISC(int index)
456 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
459 static inline MiscRegIndex
460 MISCREG_PERF_EVT_SEL(int index)
462 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
465 static inline MiscRegIndex
466 MISCREG_PERF_EVT_CTR(int index)
468 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
471 static inline MiscRegIndex
472 MISCREG_IORR_BASE(int index)
474 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
477 static inline MiscRegIndex
478 MISCREG_IORR_MASK(int index)
480 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
483 static inline MiscRegIndex
484 MISCREG_SEG_SEL(int index)
486 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
489 static inline MiscRegIndex
490 MISCREG_SEG_BASE(int index)
492 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
495 static inline MiscRegIndex
496 MISCREG_SEG_EFF_BASE(int index)
498 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
501 static inline MiscRegIndex
502 MISCREG_SEG_LIMIT(int index)
504 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
507 static inline MiscRegIndex
508 MISCREG_SEG_ATTR(int index)
510 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
513 static inline MiscRegIndex
514 MISCREG_APIC_IN_SERVICE(int index)
516 return (MiscRegIndex)(MISCREG_APIC_IN_SERVICE_BASE + index);
519 static inline MiscRegIndex
520 MISCREG_APIC_TRIGGER_MODE(int index)
522 return (MiscRegIndex)(MISCREG_APIC_TRIGGER_MODE_BASE + index);
525 static inline MiscRegIndex
526 MISCREG_APIC_INTERRUPT_REQUEST(int index)
528 return (MiscRegIndex)(MISCREG_APIC_INTERRUPT_REQUEST_BASE + index);
532 * A type to describe the condition code bits of the RFLAGS register,
533 * plus two flags, EZF and ECF, which are only visible to microcode.
535 BitUnion64(CCFlagBits)
544 EndBitUnion(CCFlagBits)
550 Bitfield<21> id; // ID Flag
551 Bitfield<20> vip; // Virtual Interrupt Pending
552 Bitfield<19> vif; // Virtual Interrupt Flag
553 Bitfield<18> ac; // Alignment Check
554 Bitfield<17> vm; // Virtual-8086 Mode
555 Bitfield<16> rf; // Resume Flag
556 Bitfield<14> nt; // Nested Task
557 Bitfield<13, 12> iopl; // I/O Privilege Level
558 Bitfield<11> of; // Overflow Flag
559 Bitfield<10> df; // Direction Flag
560 Bitfield<9> intf; // Interrupt Flag
561 Bitfield<8> tf; // Trap Flag
562 Bitfield<7> sf; // Sign Flag
563 Bitfield<6> zf; // Zero Flag
564 Bitfield<4> af; // Auxiliary Flag
565 Bitfield<2> pf; // Parity Flag
566 Bitfield<0> cf; // Carry Flag
569 BitUnion64(HandyM5Reg)
571 Bitfield<3, 1> submode;
573 EndBitUnion(HandyM5Reg)
579 Bitfield<31> pg; // Paging
580 Bitfield<30> cd; // Cache Disable
581 Bitfield<29> nw; // Not Writethrough
582 Bitfield<18> am; // Alignment Mask
583 Bitfield<16> wp; // Write Protect
584 Bitfield<5> ne; // Numeric Error
585 Bitfield<4> et; // Extension Type
586 Bitfield<3> ts; // Task Switched
587 Bitfield<2> em; // Emulation
588 Bitfield<1> mp; // Monitor Coprocessor
589 Bitfield<0> pe; // Protection Enabled
592 // Page Fault Virtual Address
594 Bitfield<31, 0> legacy;
598 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
600 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
602 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
604 Bitfield<4> pcd; // Page-Level Cache Disable
605 Bitfield<3> pwt; // Page-Level Writethrough
609 Bitfield<10> osxmmexcpt; // Operating System Unmasked
611 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
612 Bitfield<8> pce; // Performance-Monitoring Counter Enable
613 Bitfield<7> pge; // Page-Global Enable
614 Bitfield<6> mce; // Machine Check Enable
615 Bitfield<5> pae; // Physical-Address Extension
616 Bitfield<4> pse; // Page Size Extensions
617 Bitfield<3> de; // Debugging Extensions
618 Bitfield<2> tsd; // Time Stamp Disable
619 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
620 Bitfield<0> vme; // Virtual-8086 Mode Extensions
624 Bitfield<3, 0> tpr; // Task Priority Register
629 Bitfield<7, 0> vcnt; // Variable-Range Register Count
630 Bitfield<8> fix; // Fixed-Range Registers
631 Bitfield<10> wc; // Write-Combining
635 * SYSENTER configuration registers
637 BitUnion64(SysenterCS)
638 Bitfield<15, 0> targetCS;
639 EndBitUnion(SysenterCS)
641 BitUnion64(SysenterESP)
642 Bitfield<31, 0> targetESP;
643 EndBitUnion(SysenterESP)
645 BitUnion64(SysenterEIP)
646 Bitfield<31, 0> targetEIP;
647 EndBitUnion(SysenterEIP)
650 * Global machine check registers
653 Bitfield<7, 0> count; // Number of error reporting register banks
654 Bitfield<8> MCGCP; // MCG_CTL register present.
657 BitUnion64(McgStatus)
658 Bitfield<0> ripv; // Restart-IP valid
659 Bitfield<1> eipv; // Error-IP valid
660 Bitfield<2> mcip; // Machine check in-progress
661 EndBitUnion(McgStatus)
663 BitUnion64(DebugCtlMsr)
664 Bitfield<0> lbr; // Last-branch record
665 Bitfield<1> btf; // Branch single step
666 Bitfield<2> pb0; // Performance monitoring pin control 0
667 Bitfield<3> pb1; // Performance monitoring pin control 1
668 Bitfield<4> pb2; // Performance monitoring pin control 2
669 Bitfield<5> pb3; // Performance monitoring pin control 3
670 /*uint64_t pb(int index)
672 return bits(__data, index + 2);
674 EndBitUnion(DebugCtlMsr)
676 BitUnion64(MtrrPhysBase)
677 Bitfield<7, 0> type; // Default memory type
678 Bitfield<51, 12> physbase; // Range physical base address
679 EndBitUnion(MtrrPhysBase)
681 BitUnion64(MtrrPhysMask)
682 Bitfield<11> valid; // MTRR pair enable
683 Bitfield<51, 12> physmask; // Range physical mask
684 EndBitUnion(MtrrPhysMask)
686 BitUnion64(MtrrFixed)
687 /*uint64_t type(int index)
689 return bits(__data, index * 8 + 7, index * 8);
691 EndBitUnion(MtrrFixed)
694 /*uint64_t pa(int index)
696 return bits(__data, index * 8 + 2, index * 8);
700 BitUnion64(MtrrDefType)
701 Bitfield<7, 0> type; // Default type
702 Bitfield<10> fe; // Fixed range enable
703 Bitfield<11> e; // MTRR enable
704 EndBitUnion(MtrrDefType)
710 Bitfield<15,0> mcaErrorCode;
711 Bitfield<31,16> modelSpecificCode;
712 Bitfield<56,32> otherInfo;
713 Bitfield<57> pcc; // Processor-context corrupt
714 Bitfield<58> addrv; // Error-address register valid
715 Bitfield<59> miscv; // Miscellaneous-error register valid
716 Bitfield<60> en; // Error condition enabled
717 Bitfield<61> uc; // Uncorrected error
718 Bitfield<62> over; // Status register overflow
719 Bitfield<63> val; // Valid
720 EndBitUnion(McStatus)
723 /*uint64_t en(int index)
725 return bits(__data, index);
729 // Extended feature enable register
731 Bitfield<0> sce; // System call extensions
732 Bitfield<8> lme; // Long mode enable
733 Bitfield<10> lma; // Long mode active
734 Bitfield<11> nxe; // No-execute enable
735 Bitfield<12> svme; // Secure virtual machine enable
736 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
740 Bitfield<31,0> targetEip;
741 Bitfield<47,32> syscallCsAndSs;
742 Bitfield<63,48> sysretCsAndSs;
749 BitUnion64(PerfEvtSel)
750 Bitfield<7,0> eventMask;
751 Bitfield<15,8> unitMask;
752 Bitfield<16> usr; // User mode
753 Bitfield<17> os; // Operating-system mode
754 Bitfield<18> e; // Edge detect
755 Bitfield<19> pc; // Pin control
756 Bitfield<20> intEn; // Interrupt enable
757 Bitfield<22> en; // Counter enable
758 Bitfield<23> inv; // Invert mask
759 Bitfield<31,24> counterMask;
760 EndBitUnion(PerfEvtSel)
763 Bitfield<18> mfde; // MtrrFixDramEn
764 Bitfield<19> mfdm; // MtrrFixDramModEn
765 Bitfield<20> mvdm; // MtrrVarDramEn
766 Bitfield<21> tom2; // MtrrTom2En
770 Bitfield<3> wr; // WrMem Enable
771 Bitfield<4> rd; // RdMem Enable
772 Bitfield<51,12> physbase; // Range physical base address
773 EndBitUnion(IorrBase)
776 Bitfield<11> v; // I/O register pair enable (valid)
777 Bitfield<51,12> physmask; // Range physical mask
778 EndBitUnion(IorrMask)
781 Bitfield<51,23> physAddr; // Top of memory physical address
792 EndBitUnion(IgnneMsr)
794 BitUnion64(SmmCtlMsr)
797 Bitfield<2> smiCycle;
799 Bitfield<4> rsmCycle;
800 EndBitUnion(SmmCtlMsr)
805 BitUnion64(SegSelector)
806 // The following bitfield is not defined in the ISA, but it's useful
807 // when checking selectors in larger data types to make sure they
809 Bitfield<63, 3> esi; // Extended selector
810 Bitfield<15, 3> si; // Selector Index
811 Bitfield<2> ti; // Table Indicator
812 Bitfield<1, 0> rpl; // Requestor Privilege Level
813 EndBitUnion(SegSelector)
816 * Segment Descriptors
819 BitUnion64(SegDescriptor)
820 Bitfield<63, 56> baseHigh;
821 Bitfield<39, 16> baseLow;
822 Bitfield<55> g; // Granularity
823 Bitfield<54> d; // Default Operand Size
824 Bitfield<54> b; // Default Operand Size
825 Bitfield<53> l; // Long Attribute Bit
826 Bitfield<52> avl; // Available To Software
827 Bitfield<51, 48> limitHigh;
828 Bitfield<15, 0> limitLow;
829 Bitfield<47> p; // Present
830 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
831 Bitfield<44> s; // System
832 SubBitUnion(type, 43, 40)
833 // Specifies whether this descriptor is for code or data.
834 Bitfield<43> codeOrData;
836 // These bit fields are for code segments
837 Bitfield<42> c; // Conforming
838 Bitfield<41> r; // Readable
840 // These bit fields are for data segments
841 Bitfield<42> e; // Expand-Down
842 Bitfield<41> w; // Writable
844 // This is used for both code and data segments.
845 Bitfield<40> a; // Accessed
847 EndBitUnion(SegDescriptor)
850 Bitfield<0> writable;
851 Bitfield<1> readable;
852 Bitfield<2> expandDown;
854 Bitfield<5> defaultSize;
855 Bitfield<6> longMode;
858 BitUnion64(GateDescriptor)
859 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
860 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
861 Bitfield<31, 16> selector; // Target Code-Segment Selector
862 Bitfield<47> p; // Present
863 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
864 Bitfield<43, 40> type;
865 Bitfield<36, 32> count; // Parameter Count
866 EndBitUnion(GateDescriptor)
869 * Descriptor-Table Registers
888 * Local APIC Base Register
890 BitUnion64(LocalApicBase)
891 Bitfield<51, 12> base;
894 EndBitUnion(LocalApicBase)
897 #endif // __ARCH_X86_INTREGS_HH__