src/arch/x86/miscregs.hh

   1 /*
   2  * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
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   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
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  13  * teaching, education and corporate research & development.
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  19  * covered by patents for commercial use, please contact:
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  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_MISCREGS_HH__
  59 #define __ARCH_X86_MISCREGS_HH__
  60
  61 #include "arch/x86/apicregs.hh"
  62 #include "arch/x86/segmentregs.hh"
  63 #include "arch/x86/x86_traits.hh"
  64 #include "base/bitunion.hh"
  65
  66 //These get defined in some system headers (at least termbits.h). That confuses
  67 //things here significantly.
  68 #undef CR0
  69 #undef CR2
  70 #undef CR3
  71
  72 namespace X86ISA
  73 {
  74     enum CondFlagBit {
  75         CFBit = 1 << 0,
  76         PFBit = 1 << 2,
  77         ECFBit = 1 << 3,
  78         AFBit = 1 << 4,
  79         EZFBit = 1 << 5,
  80         ZFBit = 1 << 6,
  81         SFBit = 1 << 7,
  82         DFBit = 1 << 10,
  83         OFBit = 1 << 11
  84     };
  85
  86     enum RFLAGBit {
  87         TFBit = 1 << 8,
  88         IFBit = 1 << 9,
  89         NTBit = 1 << 14,
  90         RFBit = 1 << 16,
  91         VMBit = 1 << 17,
  92         ACBit = 1 << 18,
  93         VIFBit = 1 << 19,
  94         VIPBit = 1 << 20,
  95         IDBit = 1 << 21
  96     };
  97
  98     enum MiscRegIndex
  99     {
 100         // Control registers
 101         // Most of these are invalid.
 102         MISCREG_CR_BASE,
 103         MISCREG_CR0 = MISCREG_CR_BASE,
 104         MISCREG_CR1,
 105         MISCREG_CR2,
 106         MISCREG_CR3,
 107         MISCREG_CR4,
 108         MISCREG_CR5,
 109         MISCREG_CR6,
 110         MISCREG_CR7,
 111         MISCREG_CR8,
 112         MISCREG_CR9,
 113         MISCREG_CR10,
 114         MISCREG_CR11,
 115         MISCREG_CR12,
 116         MISCREG_CR13,
 117         MISCREG_CR14,
 118         MISCREG_CR15,
 119
 120         // Debug registers
 121         MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
 122         MISCREG_DR0 = MISCREG_DR_BASE,
 123         MISCREG_DR1,
 124         MISCREG_DR2,
 125         MISCREG_DR3,
 126         MISCREG_DR4,
 127         MISCREG_DR5,
 128         MISCREG_DR6,
 129         MISCREG_DR7,
 130
 131         // Flags register
 132         MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
 133
 134         //Register to keep handy values like the CPU mode in.
 135         MISCREG_M5_REG,
 136
 137         /*
 138          * Model Specific Registers
 139          */
 140         // Time stamp counter
 141         MISCREG_TSC,
 142
 143         MISCREG_MTRRCAP,
 144
 145         MISCREG_SYSENTER_CS,
 146         MISCREG_SYSENTER_ESP,
 147         MISCREG_SYSENTER_EIP,
 148
 149         MISCREG_MCG_CAP,
 150         MISCREG_MCG_STATUS,
 151         MISCREG_MCG_CTL,
 152
 153         MISCREG_DEBUG_CTL_MSR,
 154
 155         MISCREG_LAST_BRANCH_FROM_IP,
 156         MISCREG_LAST_BRANCH_TO_IP,
 157         MISCREG_LAST_EXCEPTION_FROM_IP,
 158         MISCREG_LAST_EXCEPTION_TO_IP,
 159
 160         MISCREG_MTRR_PHYS_BASE_BASE,
 161         MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
 162         MISCREG_MTRR_PHYS_BASE_1,
 163         MISCREG_MTRR_PHYS_BASE_2,
 164         MISCREG_MTRR_PHYS_BASE_3,
 165         MISCREG_MTRR_PHYS_BASE_4,
 166         MISCREG_MTRR_PHYS_BASE_5,
 167         MISCREG_MTRR_PHYS_BASE_6,
 168         MISCREG_MTRR_PHYS_BASE_7,
 169
 170         MISCREG_MTRR_PHYS_MASK_BASE,
 171         MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
 172         MISCREG_MTRR_PHYS_MASK_1,
 173         MISCREG_MTRR_PHYS_MASK_2,
 174         MISCREG_MTRR_PHYS_MASK_3,
 175         MISCREG_MTRR_PHYS_MASK_4,
 176         MISCREG_MTRR_PHYS_MASK_5,
 177         MISCREG_MTRR_PHYS_MASK_6,
 178         MISCREG_MTRR_PHYS_MASK_7,
 179
 180         MISCREG_MTRR_FIX_64K_00000,
 181         MISCREG_MTRR_FIX_16K_80000,
 182         MISCREG_MTRR_FIX_16K_A0000,
 183         MISCREG_MTRR_FIX_4K_C0000,
 184         MISCREG_MTRR_FIX_4K_C8000,
 185         MISCREG_MTRR_FIX_4K_D0000,
 186         MISCREG_MTRR_FIX_4K_D8000,
 187         MISCREG_MTRR_FIX_4K_E0000,
 188         MISCREG_MTRR_FIX_4K_E8000,
 189         MISCREG_MTRR_FIX_4K_F0000,
 190         MISCREG_MTRR_FIX_4K_F8000,
 191
 192         MISCREG_PAT,
 193
 194         MISCREG_DEF_TYPE,
 195
 196         MISCREG_MC_CTL_BASE,
 197         MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
 198         MISCREG_MC1_CTL,
 199         MISCREG_MC2_CTL,
 200         MISCREG_MC3_CTL,
 201         MISCREG_MC4_CTL,
 202         MISCREG_MC5_CTL,
 203         MISCREG_MC6_CTL,
 204         MISCREG_MC7_CTL,
 205
 206         MISCREG_MC_STATUS_BASE,
 207         MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
 208         MISCREG_MC1_STATUS,
 209         MISCREG_MC2_STATUS,
 210         MISCREG_MC3_STATUS,
 211         MISCREG_MC4_STATUS,
 212         MISCREG_MC5_STATUS,
 213         MISCREG_MC6_STATUS,
 214         MISCREG_MC7_STATUS,
 215
 216         MISCREG_MC_ADDR_BASE,
 217         MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
 218         MISCREG_MC1_ADDR,
 219         MISCREG_MC2_ADDR,
 220         MISCREG_MC3_ADDR,
 221         MISCREG_MC4_ADDR,
 222         MISCREG_MC5_ADDR,
 223         MISCREG_MC6_ADDR,
 224         MISCREG_MC7_ADDR,
 225
 226         MISCREG_MC_MISC_BASE,
 227         MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
 228         MISCREG_MC1_MISC,
 229         MISCREG_MC2_MISC,
 230         MISCREG_MC3_MISC,
 231         MISCREG_MC4_MISC,
 232         MISCREG_MC5_MISC,
 233         MISCREG_MC6_MISC,
 234         MISCREG_MC7_MISC,
 235
 236         // Extended feature enable register
 237         MISCREG_EFER,
 238
 239         MISCREG_STAR,
 240         MISCREG_LSTAR,
 241         MISCREG_CSTAR,
 242
 243         MISCREG_SF_MASK,
 244
 245         MISCREG_KERNEL_GS_BASE,
 246
 247         MISCREG_TSC_AUX,
 248
 249         MISCREG_PERF_EVT_SEL_BASE,
 250         MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
 251         MISCREG_PERF_EVT_SEL1,
 252         MISCREG_PERF_EVT_SEL2,
 253         MISCREG_PERF_EVT_SEL3,
 254
 255         MISCREG_PERF_EVT_CTR_BASE,
 256         MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
 257         MISCREG_PERF_EVT_CTR1,
 258         MISCREG_PERF_EVT_CTR2,
 259         MISCREG_PERF_EVT_CTR3,
 260
 261         MISCREG_SYSCFG,
 262
 263         MISCREG_IORR_BASE_BASE,
 264         MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
 265         MISCREG_IORR_BASE1,
 266
 267         MISCREG_IORR_MASK_BASE,
 268         MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
 269         MISCREG_IORR_MASK1,
 270
 271         MISCREG_TOP_MEM,
 272         MISCREG_TOP_MEM2,
 273
 274         MISCREG_VM_CR,
 275         MISCREG_IGNNE,
 276         MISCREG_SMM_CTL,
 277         MISCREG_VM_HSAVE_PA,
 278
 279         /*
 280          * Segment registers
 281          */
 282         // Segment selectors
 283         MISCREG_SEG_SEL_BASE,
 284         MISCREG_ES = MISCREG_SEG_SEL_BASE,
 285         MISCREG_CS,
 286         MISCREG_SS,
 287         MISCREG_DS,
 288         MISCREG_FS,
 289         MISCREG_GS,
 290         MISCREG_HS,
 291         MISCREG_TSL,
 292         MISCREG_TSG,
 293         MISCREG_LS,
 294         MISCREG_MS,
 295         MISCREG_TR,
 296         MISCREG_IDTR,
 297
 298         // Hidden segment base field
 299         MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
 300         MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
 301         MISCREG_CS_BASE,
 302         MISCREG_SS_BASE,
 303         MISCREG_DS_BASE,
 304         MISCREG_FS_BASE,
 305         MISCREG_GS_BASE,
 306         MISCREG_HS_BASE,
 307         MISCREG_TSL_BASE,
 308         MISCREG_TSG_BASE,
 309         MISCREG_LS_BASE,
 310         MISCREG_MS_BASE,
 311         MISCREG_TR_BASE,
 312         MISCREG_IDTR_BASE,
 313
 314         // The effective segment base, ie what is actually added to an
 315         // address. In 64 bit mode this can be different from the above,
 316         // namely 0.
 317         MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
 318         MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
 319         MISCREG_CS_EFF_BASE,
 320         MISCREG_SS_EFF_BASE,
 321         MISCREG_DS_EFF_BASE,
 322         MISCREG_FS_EFF_BASE,
 323         MISCREG_GS_EFF_BASE,
 324         MISCREG_HS_EFF_BASE,
 325         MISCREG_TSL_EFF_BASE,
 326         MISCREG_TSG_EFF_BASE,
 327         MISCREG_LS_EFF_BASE,
 328         MISCREG_MS_EFF_BASE,
 329         MISCREG_TR_EFF_BASE,
 330         MISCREG_IDTR_EFF_BASE,
 331
 332         // Hidden segment limit field
 333         MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
 334         MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
 335         MISCREG_CS_LIMIT,
 336         MISCREG_SS_LIMIT,
 337         MISCREG_DS_LIMIT,
 338         MISCREG_FS_LIMIT,
 339         MISCREG_GS_LIMIT,
 340         MISCREG_HS_LIMIT,
 341         MISCREG_TSL_LIMIT,
 342         MISCREG_TSG_LIMIT,
 343         MISCREG_LS_LIMIT,
 344         MISCREG_MS_LIMIT,
 345         MISCREG_TR_LIMIT,
 346         MISCREG_IDTR_LIMIT,
 347
 348         // Hidden segment limit attributes
 349         MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
 350         MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
 351         MISCREG_CS_ATTR,
 352         MISCREG_SS_ATTR,
 353         MISCREG_DS_ATTR,
 354         MISCREG_FS_ATTR,
 355         MISCREG_GS_ATTR,
 356         MISCREG_HS_ATTR,
 357         MISCREG_TSL_ATTR,
 358         MISCREG_TSG_ATTR,
 359         MISCREG_LS_ATTR,
 360         MISCREG_MS_ATTR,
 361         MISCREG_TR_ATTR,
 362         MISCREG_IDTR_ATTR,
 363
 364         // Floating point control registers
 365         MISCREG_X87_TOP =
 366             MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
 367
 368         //XXX Add "Model-Specific Registers"
 369
 370         MISCREG_APIC_BASE,
 371
 372         // Space for the APIC registers
 373         MISCREG_APIC_START,
 374         MISCREG_APIC_END = MISCREG_APIC_START + NUM_APIC_REGS - 1,
 375
 376         // "Fake" MSRs for internally implemented devices
 377         MISCREG_PCI_CONFIG_ADDRESS,
 378
 379         NUM_MISCREGS
 380     };
 381
 382     static inline bool
 383     isApicReg(MiscRegIndex index)
 384     {
 385         return index >= MISCREG_APIC_START && index <= MISCREG_APIC_END;
 386     }
 387
 388     static inline MiscRegIndex
 389     MISCREG_CR(int index)
 390     {
 391         return (MiscRegIndex)(MISCREG_CR_BASE + index);
 392     }
 393
 394     static inline MiscRegIndex
 395     MISCREG_DR(int index)
 396     {
 397         return (MiscRegIndex)(MISCREG_DR_BASE + index);
 398     }
 399
 400     static inline MiscRegIndex
 401     MISCREG_MTRR_PHYS_BASE(int index)
 402     {
 403         return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
 404     }
 405
 406     static inline MiscRegIndex
 407     MISCREG_MTRR_PHYS_MASK(int index)
 408     {
 409         return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
 410     }
 411
 412     static inline MiscRegIndex
 413     MISCREG_MC_CTL(int index)
 414     {
 415         return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
 416     }
 417
 418     static inline MiscRegIndex
 419     MISCREG_MC_STATUS(int index)
 420     {
 421         return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
 422     }
 423
 424     static inline MiscRegIndex
 425     MISCREG_MC_ADDR(int index)
 426     {
 427         return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
 428     }
 429
 430     static inline MiscRegIndex
 431     MISCREG_MC_MISC(int index)
 432     {
 433         return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
 434     }
 435
 436     static inline MiscRegIndex
 437     MISCREG_PERF_EVT_SEL(int index)
 438     {
 439         return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
 440     }
 441
 442     static inline MiscRegIndex
 443     MISCREG_PERF_EVT_CTR(int index)
 444     {
 445         return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
 446     }
 447
 448     static inline MiscRegIndex
 449     MISCREG_IORR_BASE(int index)
 450     {
 451         return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
 452     }
 453
 454     static inline MiscRegIndex
 455     MISCREG_IORR_MASK(int index)
 456     {
 457         return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
 458     }
 459
 460     static inline MiscRegIndex
 461     MISCREG_SEG_SEL(int index)
 462     {
 463         return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
 464     }
 465
 466     static inline MiscRegIndex
 467     MISCREG_SEG_BASE(int index)
 468     {
 469         return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
 470     }
 471
 472     static inline MiscRegIndex
 473     MISCREG_SEG_EFF_BASE(int index)
 474     {
 475         return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
 476     }
 477
 478     static inline MiscRegIndex
 479     MISCREG_SEG_LIMIT(int index)
 480     {
 481         return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
 482     }
 483
 484     static inline MiscRegIndex
 485     MISCREG_SEG_ATTR(int index)
 486     {
 487         return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
 488     }
 489
 490     /**
 491      * A type to describe the condition code bits of the RFLAGS register,
 492      * plus two flags, EZF and ECF, which are only visible to microcode.
 493      */
 494     BitUnion64(CCFlagBits)
 495         Bitfield<11> of;
 496         Bitfield<7> sf;
 497         Bitfield<6> zf;
 498         Bitfield<5> ezf;
 499         Bitfield<4> af;
 500         Bitfield<3> ecf;
 501         Bitfield<2> pf;
 502         Bitfield<0> cf;
 503     EndBitUnion(CCFlagBits)
 504
 505     /**
 506      * RFLAGS
 507      */
 508     BitUnion64(RFLAGS)
 509         Bitfield<21> id; // ID Flag
 510         Bitfield<20> vip; // Virtual Interrupt Pending
 511         Bitfield<19> vif; // Virtual Interrupt Flag
 512         Bitfield<18> ac; // Alignment Check
 513         Bitfield<17> vm; // Virtual-8086 Mode
 514         Bitfield<16> rf; // Resume Flag
 515         Bitfield<14> nt; // Nested Task
 516         Bitfield<13, 12> iopl; // I/O Privilege Level
 517         Bitfield<11> of; // Overflow Flag
 518         Bitfield<10> df; // Direction Flag
 519         Bitfield<9> intf; // Interrupt Flag
 520         Bitfield<8> tf; // Trap Flag
 521         Bitfield<7> sf; // Sign Flag
 522         Bitfield<6> zf; // Zero Flag
 523         Bitfield<4> af; // Auxiliary Flag
 524         Bitfield<2> pf; // Parity Flag
 525         Bitfield<0> cf; // Carry Flag
 526     EndBitUnion(RFLAGS)
 527
 528     BitUnion64(HandyM5Reg)
 529         Bitfield<0> mode;
 530         Bitfield<3, 1> submode;
 531         Bitfield<5, 4> cpl;
 532     EndBitUnion(HandyM5Reg)
 533
 534     /**
 535      * Control registers
 536      */
 537     BitUnion64(CR0)
 538         Bitfield<31> pg; // Paging
 539         Bitfield<30> cd; // Cache Disable
 540         Bitfield<29> nw; // Not Writethrough
 541         Bitfield<18> am; // Alignment Mask
 542         Bitfield<16> wp; // Write Protect
 543         Bitfield<5> ne; // Numeric Error
 544         Bitfield<4> et; // Extension Type
 545         Bitfield<3> ts; // Task Switched
 546         Bitfield<2> em; // Emulation
 547         Bitfield<1> mp; // Monitor Coprocessor
 548         Bitfield<0> pe; // Protection Enabled
 549     EndBitUnion(CR0)
 550
 551     // Page Fault Virtual Address
 552     BitUnion64(CR2)
 553         Bitfield<31, 0> legacy;
 554     EndBitUnion(CR2)
 555
 556     BitUnion64(CR3)
 557         Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
 558                                    // Base Address
 559         Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
 560                                // Base Address
 561         Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
 562                                  // Base Address
 563         Bitfield<4> pcd; // Page-Level Cache Disable
 564         Bitfield<3> pwt; // Page-Level Writethrough
 565     EndBitUnion(CR3)
 566
 567     BitUnion64(CR4)
 568         Bitfield<10> osxmmexcpt; // Operating System Unmasked
 569                                  // Exception Support
 570         Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
 571         Bitfield<8> pce; // Performance-Monitoring Counter Enable
 572         Bitfield<7> pge; // Page-Global Enable
 573         Bitfield<6> mce; // Machine Check Enable
 574         Bitfield<5> pae; // Physical-Address Extension
 575         Bitfield<4> pse; // Page Size Extensions
 576         Bitfield<3> de; // Debugging Extensions
 577         Bitfield<2> tsd; // Time Stamp Disable
 578         Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
 579         Bitfield<0> vme; // Virtual-8086 Mode Extensions
 580     EndBitUnion(CR4)
 581
 582     BitUnion64(CR8)
 583         Bitfield<3, 0> tpr; // Task Priority Register
 584     EndBitUnion(CR8)
 585
 586     // MTRR capabilities
 587     BitUnion64(MTRRcap)
 588         Bitfield<7, 0> vcnt; // Variable-Range Register Count
 589         Bitfield<8> fix; // Fixed-Range Registers
 590         Bitfield<10> wc; // Write-Combining
 591     EndBitUnion(MTRRcap)
 592
 593     /**
 594      * SYSENTER configuration registers
 595      */
 596     BitUnion64(SysenterCS)
 597         Bitfield<15, 0> targetCS;
 598     EndBitUnion(SysenterCS)
 599
 600     BitUnion64(SysenterESP)
 601         Bitfield<31, 0> targetESP;
 602     EndBitUnion(SysenterESP)
 603
 604     BitUnion64(SysenterEIP)
 605         Bitfield<31, 0> targetEIP;
 606     EndBitUnion(SysenterEIP)
 607
 608     /**
 609      * Global machine check registers
 610      */
 611     BitUnion64(McgCap)
 612         Bitfield<7, 0> count; // Number of error reporting register banks
 613         Bitfield<8> MCGCP; // MCG_CTL register present.
 614     EndBitUnion(McgCap)
 615
 616     BitUnion64(McgStatus)
 617         Bitfield<0> ripv; // Restart-IP valid
 618         Bitfield<1> eipv; // Error-IP valid
 619         Bitfield<2> mcip; // Machine check in-progress
 620     EndBitUnion(McgStatus)
 621
 622     BitUnion64(DebugCtlMsr)
 623         Bitfield<0> lbr; // Last-branch record
 624         Bitfield<1> btf; // Branch single step
 625         Bitfield<2> pb0; // Performance monitoring pin control 0
 626         Bitfield<3> pb1; // Performance monitoring pin control 1
 627         Bitfield<4> pb2; // Performance monitoring pin control 2
 628         Bitfield<5> pb3; // Performance monitoring pin control 3
 629         /*uint64_t pb(int index)
 630         {
 631             return bits(__data, index + 2);
 632         }*/
 633     EndBitUnion(DebugCtlMsr)
 634
 635     BitUnion64(MtrrPhysBase)
 636         Bitfield<7, 0> type; // Default memory type
 637         Bitfield<51, 12> physbase; // Range physical base address
 638     EndBitUnion(MtrrPhysBase)
 639
 640     BitUnion64(MtrrPhysMask)
 641         Bitfield<11> valid; // MTRR pair enable
 642         Bitfield<51, 12> physmask; // Range physical mask
 643     EndBitUnion(MtrrPhysMask)
 644
 645     BitUnion64(MtrrFixed)
 646         /*uint64_t type(int index)
 647         {
 648             return bits(__data, index * 8 + 7, index * 8);
 649         }*/
 650     EndBitUnion(MtrrFixed)
 651
 652     BitUnion64(Pat)
 653         /*uint64_t pa(int index)
 654         {
 655             return bits(__data, index * 8 + 2, index * 8);
 656         }*/
 657     EndBitUnion(Pat)
 658
 659     BitUnion64(MtrrDefType)
 660         Bitfield<7, 0> type; // Default type
 661         Bitfield<10> fe; // Fixed range enable
 662         Bitfield<11> e; // MTRR enable
 663     EndBitUnion(MtrrDefType)
 664
 665     /**
 666      * Machine check
 667      */
 668     BitUnion64(McStatus)
 669         Bitfield<15,0> mcaErrorCode;
 670         Bitfield<31,16> modelSpecificCode;
 671         Bitfield<56,32> otherInfo;
 672         Bitfield<57> pcc; // Processor-context corrupt
 673         Bitfield<58> addrv; // Error-address register valid
 674         Bitfield<59> miscv; // Miscellaneous-error register valid
 675         Bitfield<60> en; // Error condition enabled
 676         Bitfield<61> uc; // Uncorrected error
 677         Bitfield<62> over; // Status register overflow
 678         Bitfield<63> val; // Valid
 679     EndBitUnion(McStatus)
 680
 681     BitUnion64(McCtl)
 682         /*uint64_t en(int index)
 683         {
 684             return bits(__data, index);
 685         }*/
 686     EndBitUnion(McCtl)
 687
 688     // Extended feature enable register
 689     BitUnion64(Efer)
 690         Bitfield<0> sce; // System call extensions
 691         Bitfield<8> lme; // Long mode enable
 692         Bitfield<10> lma; // Long mode active
 693         Bitfield<11> nxe; // No-execute enable
 694         Bitfield<12> svme; // Secure virtual machine enable
 695         Bitfield<14> ffxsr; // Fast fxsave/fxrstor
 696     EndBitUnion(Efer)
 697
 698     BitUnion64(Star)
 699         Bitfield<31,0> targetEip;
 700         Bitfield<47,32> syscallCsAndSs;
 701         Bitfield<63,48> sysretCsAndSs;
 702     EndBitUnion(Star)
 703
 704     BitUnion64(SfMask)
 705         Bitfield<31,0> mask;
 706     EndBitUnion(SfMask)
 707
 708     BitUnion64(PerfEvtSel)
 709         Bitfield<7,0> eventMask;
 710         Bitfield<15,8> unitMask;
 711         Bitfield<16> usr; // User mode
 712         Bitfield<17> os; // Operating-system mode
 713         Bitfield<18> e; // Edge detect
 714         Bitfield<19> pc; // Pin control
 715         Bitfield<20> intEn; // Interrupt enable
 716         Bitfield<22> en; // Counter enable
 717         Bitfield<23> inv; // Invert mask
 718         Bitfield<31,24> counterMask;
 719     EndBitUnion(PerfEvtSel)
 720
 721     BitUnion32(Syscfg)
 722         Bitfield<18> mfde; // MtrrFixDramEn
 723         Bitfield<19> mfdm; // MtrrFixDramModEn
 724         Bitfield<20> mvdm; // MtrrVarDramEn
 725         Bitfield<21> tom2; // MtrrTom2En
 726     EndBitUnion(Syscfg)
 727
 728     BitUnion64(IorrBase)
 729         Bitfield<3> wr; // WrMem Enable
 730         Bitfield<4> rd; // RdMem Enable
 731         Bitfield<51,12> physbase; // Range physical base address
 732     EndBitUnion(IorrBase)
 733
 734     BitUnion64(IorrMask)
 735         Bitfield<11> v; // I/O register pair enable (valid)
 736         Bitfield<51,12> physmask; // Range physical mask
 737     EndBitUnion(IorrMask)
 738
 739     BitUnion64(Tom)
 740         Bitfield<51,23> physAddr; // Top of memory physical address
 741     EndBitUnion(Tom)
 742
 743     BitUnion64(VmCrMsr)
 744         Bitfield<0> dpd;
 745         Bitfield<1> rInit;
 746         Bitfield<2> disA20M;
 747     EndBitUnion(VmCrMsr)
 748
 749     BitUnion64(IgnneMsr)
 750         Bitfield<0> ignne;
 751     EndBitUnion(IgnneMsr)
 752
 753     BitUnion64(SmmCtlMsr)
 754         Bitfield<0> dismiss;
 755         Bitfield<1> enter;
 756         Bitfield<2> smiCycle;
 757         Bitfield<3> exit;
 758         Bitfield<4> rsmCycle;
 759     EndBitUnion(SmmCtlMsr)
 760
 761     /**
 762      * Segment Selector
 763      */
 764     BitUnion64(SegSelector)
 765         // The following bitfield is not defined in the ISA, but it's useful
 766         // when checking selectors in larger data types to make sure they
 767         // aren't too large.
 768         Bitfield<63, 3> esi; // Extended selector
 769         Bitfield<15, 3> si; // Selector Index
 770         Bitfield<2> ti; // Table Indicator
 771         Bitfield<1, 0> rpl; // Requestor Privilege Level
 772     EndBitUnion(SegSelector)
 773
 774     /**
 775      * Segment Descriptors
 776      */
 777
 778     BitUnion64(SegDescriptor)
 779         Bitfield<63, 56> baseHigh;
 780         Bitfield<39, 16> baseLow;
 781         Bitfield<55> g; // Granularity
 782         Bitfield<54> d; // Default Operand Size
 783         Bitfield<54> b; // Default Operand Size
 784         Bitfield<53> l; // Long Attribute Bit
 785         Bitfield<52> avl; // Available To Software
 786         Bitfield<51, 48> limitHigh;
 787         Bitfield<15, 0> limitLow;
 788         Bitfield<47> p; // Present
 789         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 790         Bitfield<44> s; // System
 791         SubBitUnion(type, 43, 40)
 792             // Specifies whether this descriptor is for code or data.
 793             Bitfield<43> codeOrData;
 794
 795             // These bit fields are for code segments
 796             Bitfield<42> c; // Conforming
 797             Bitfield<41> r; // Readable
 798
 799             // These bit fields are for data segments
 800             Bitfield<42> e; // Expand-Down
 801             Bitfield<41> w; // Writable
 802
 803             // This is used for both code and data segments.
 804             Bitfield<40> a; // Accessed
 805         EndSubBitUnion(type)
 806     EndBitUnion(SegDescriptor)
 807
 808     BitUnion64(SegAttr)
 809         Bitfield<0> writable;
 810         Bitfield<1> readable;
 811         Bitfield<2> expandDown;
 812         Bitfield<4, 3> dpl;
 813         Bitfield<5> defaultSize;
 814         Bitfield<6> longMode;
 815     EndBitUnion(SegAttr)
 816
 817     BitUnion64(GateDescriptor)
 818         Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
 819         Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
 820         Bitfield<31, 16> selector; // Target Code-Segment Selector
 821         Bitfield<47> p; // Present
 822         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 823         Bitfield<43, 40> type;
 824         Bitfield<36, 32> count; // Parameter Count
 825     EndBitUnion(GateDescriptor)
 826
 827     /**
 828      * Descriptor-Table Registers
 829      */
 830     BitUnion64(GDTR)
 831     EndBitUnion(GDTR)
 832
 833     BitUnion64(IDTR)
 834     EndBitUnion(IDTR)
 835
 836     BitUnion64(LDTR)
 837     EndBitUnion(LDTR)
 838
 839     /**
 840      * Task Register
 841      */
 842     BitUnion64(TR)
 843     EndBitUnion(TR)
 844
 845
 846     /**
 847      * Local APIC Base Register
 848      */
 849     BitUnion64(LocalApicBase)
 850         Bitfield<51, 12> base;
 851         Bitfield<11> enable;
 852         Bitfield<8> bsp;
 853     EndBitUnion(LocalApicBase)
 854 };
 855
 856 #endif // __ARCH_X86_INTREGS_HH__