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58 #ifndef __ARCH_X86_MISCREGS_HH__
59 #define __ARCH_X86_MISCREGS_HH__
61 #include "arch/x86/segmentregs.hh"
62 #include "arch/x86/x86_traits.hh"
63 #include "base/bitunion.hh"
65 //These get defined in some system headers (at least termbits.h). That confuses
66 //things here significantly.
100 // Most of these are invalid.
102 MISCREG_CR0 = MISCREG_CR_BASE,
120 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
121 MISCREG_DR0 = MISCREG_DR_BASE,
131 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
133 //Register to keep handy values like the CPU mode in.
137 * Model Specific Registers
139 // Time stamp counter
145 MISCREG_SYSENTER_ESP,
146 MISCREG_SYSENTER_EIP,
152 MISCREG_DEBUG_CTL_MSR,
154 MISCREG_LAST_BRANCH_FROM_IP,
155 MISCREG_LAST_BRANCH_TO_IP,
156 MISCREG_LAST_EXCEPTION_FROM_IP,
157 MISCREG_LAST_EXCEPTION_TO_IP,
159 MISCREG_MTRR_PHYS_BASE_BASE,
160 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
161 MISCREG_MTRR_PHYS_BASE_1,
162 MISCREG_MTRR_PHYS_BASE_2,
163 MISCREG_MTRR_PHYS_BASE_3,
164 MISCREG_MTRR_PHYS_BASE_4,
165 MISCREG_MTRR_PHYS_BASE_5,
166 MISCREG_MTRR_PHYS_BASE_6,
167 MISCREG_MTRR_PHYS_BASE_7,
168 MISCREG_MTRR_PHYS_BASE_END,
170 MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END,
171 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
172 MISCREG_MTRR_PHYS_MASK_1,
173 MISCREG_MTRR_PHYS_MASK_2,
174 MISCREG_MTRR_PHYS_MASK_3,
175 MISCREG_MTRR_PHYS_MASK_4,
176 MISCREG_MTRR_PHYS_MASK_5,
177 MISCREG_MTRR_PHYS_MASK_6,
178 MISCREG_MTRR_PHYS_MASK_7,
179 MISCREG_MTRR_PHYS_MASK_END,
181 MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END,
182 MISCREG_MTRR_FIX_16K_80000,
183 MISCREG_MTRR_FIX_16K_A0000,
184 MISCREG_MTRR_FIX_4K_C0000,
185 MISCREG_MTRR_FIX_4K_C8000,
186 MISCREG_MTRR_FIX_4K_D0000,
187 MISCREG_MTRR_FIX_4K_D8000,
188 MISCREG_MTRR_FIX_4K_E0000,
189 MISCREG_MTRR_FIX_4K_E8000,
190 MISCREG_MTRR_FIX_4K_F0000,
191 MISCREG_MTRR_FIX_4K_F8000,
198 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
208 MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END,
209 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
217 MISCREG_MC_STATUS_END,
219 MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END,
220 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
230 MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END,
231 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
241 // Extended feature enable register
242 MISCREG_EFER = MISCREG_MC_MISC_END,
250 MISCREG_KERNEL_GS_BASE,
254 MISCREG_PERF_EVT_SEL_BASE,
255 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
256 MISCREG_PERF_EVT_SEL1,
257 MISCREG_PERF_EVT_SEL2,
258 MISCREG_PERF_EVT_SEL3,
259 MISCREG_PERF_EVT_SEL_END,
261 MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END,
262 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
263 MISCREG_PERF_EVT_CTR1,
264 MISCREG_PERF_EVT_CTR2,
265 MISCREG_PERF_EVT_CTR3,
266 MISCREG_PERF_EVT_CTR_END,
268 MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END,
270 MISCREG_IORR_BASE_BASE,
271 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
273 MISCREG_IORR_BASE_END,
275 MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END,
276 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
278 MISCREG_IORR_MASK_END,
280 MISCREG_TOP_MEM = MISCREG_IORR_MASK_END,
292 MISCREG_SEG_SEL_BASE,
293 MISCREG_ES = MISCREG_SEG_SEL_BASE,
307 // Hidden segment base field
308 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
309 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
323 // The effective segment base, ie what is actually added to an
324 // address. In 64 bit mode this can be different from the above,
326 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
327 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
334 MISCREG_TSL_EFF_BASE,
335 MISCREG_TSG_EFF_BASE,
339 MISCREG_IDTR_EFF_BASE,
341 // Hidden segment limit field
342 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
343 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
357 // Hidden segment limit attributes
358 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
359 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
373 // Floating point control registers
375 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
377 //XXX Add "Model-Specific Registers"
381 // "Fake" MSRs for internally implemented devices
382 MISCREG_PCI_CONFIG_ADDRESS,
387 static inline MiscRegIndex
388 MISCREG_CR(int index)
390 assert(index >= 0 && index < NumCRegs);
391 return (MiscRegIndex)(MISCREG_CR_BASE + index);
394 static inline MiscRegIndex
395 MISCREG_DR(int index)
397 assert(index >= 0 && index < NumDRegs);
398 return (MiscRegIndex)(MISCREG_DR_BASE + index);
401 static inline MiscRegIndex
402 MISCREG_MTRR_PHYS_BASE(int index)
404 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
405 MISCREG_MTRR_PHYS_BASE_BASE));
406 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
409 static inline MiscRegIndex
410 MISCREG_MTRR_PHYS_MASK(int index)
412 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
413 MISCREG_MTRR_PHYS_MASK_BASE));
414 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
417 static inline MiscRegIndex
418 MISCREG_MC_CTL(int index)
420 assert(index >= 0 && index < (MISCREG_MC_CTL_END -
421 MISCREG_MC_CTL_BASE));
422 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
425 static inline MiscRegIndex
426 MISCREG_MC_STATUS(int index)
428 assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
429 MISCREG_MC_STATUS_BASE));
430 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
433 static inline MiscRegIndex
434 MISCREG_MC_ADDR(int index)
436 assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
437 MISCREG_MC_ADDR_BASE));
438 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
441 static inline MiscRegIndex
442 MISCREG_MC_MISC(int index)
444 assert(index >= 0 && index < (MISCREG_MC_MISC_END -
445 MISCREG_MC_MISC_BASE));
446 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
449 static inline MiscRegIndex
450 MISCREG_PERF_EVT_SEL(int index)
452 assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
453 MISCREG_PERF_EVT_SEL_BASE));
454 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
457 static inline MiscRegIndex
458 MISCREG_PERF_EVT_CTR(int index)
460 assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END -
461 MISCREG_PERF_EVT_CTR_BASE));
462 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
465 static inline MiscRegIndex
466 MISCREG_IORR_BASE(int index)
468 assert(index >= 0 && index < (MISCREG_IORR_BASE_END -
469 MISCREG_IORR_BASE_BASE));
470 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
473 static inline MiscRegIndex
474 MISCREG_IORR_MASK(int index)
476 assert(index >= 0 && index < (MISCREG_IORR_MASK_END -
477 MISCREG_IORR_MASK_BASE));
478 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
481 static inline MiscRegIndex
482 MISCREG_SEG_SEL(int index)
484 assert(index >= 0 && index < NUM_SEGMENTREGS);
485 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
488 static inline MiscRegIndex
489 MISCREG_SEG_BASE(int index)
491 assert(index >= 0 && index < NUM_SEGMENTREGS);
492 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
495 static inline MiscRegIndex
496 MISCREG_SEG_EFF_BASE(int index)
498 assert(index >= 0 && index < NUM_SEGMENTREGS);
499 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
502 static inline MiscRegIndex
503 MISCREG_SEG_LIMIT(int index)
505 assert(index >= 0 && index < NUM_SEGMENTREGS);
506 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
509 static inline MiscRegIndex
510 MISCREG_SEG_ATTR(int index)
512 assert(index >= 0 && index < NUM_SEGMENTREGS);
513 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
517 * A type to describe the condition code bits of the RFLAGS register,
518 * plus two flags, EZF and ECF, which are only visible to microcode.
520 BitUnion64(CCFlagBits)
529 EndBitUnion(CCFlagBits)
535 Bitfield<21> id; // ID Flag
536 Bitfield<20> vip; // Virtual Interrupt Pending
537 Bitfield<19> vif; // Virtual Interrupt Flag
538 Bitfield<18> ac; // Alignment Check
539 Bitfield<17> vm; // Virtual-8086 Mode
540 Bitfield<16> rf; // Resume Flag
541 Bitfield<14> nt; // Nested Task
542 Bitfield<13, 12> iopl; // I/O Privilege Level
543 Bitfield<11> of; // Overflow Flag
544 Bitfield<10> df; // Direction Flag
545 Bitfield<9> intf; // Interrupt Flag
546 Bitfield<8> tf; // Trap Flag
547 Bitfield<7> sf; // Sign Flag
548 Bitfield<6> zf; // Zero Flag
549 Bitfield<4> af; // Auxiliary Flag
550 Bitfield<2> pf; // Parity Flag
551 Bitfield<0> cf; // Carry Flag
554 BitUnion64(HandyM5Reg)
556 Bitfield<3, 1> submode;
560 Bitfield<9, 8> defOp;
561 Bitfield<11, 10> altOp;
562 Bitfield<13, 12> defAddr;
563 Bitfield<15, 14> altAddr;
564 Bitfield<17, 16> stack;
565 EndBitUnion(HandyM5Reg)
571 Bitfield<31> pg; // Paging
572 Bitfield<30> cd; // Cache Disable
573 Bitfield<29> nw; // Not Writethrough
574 Bitfield<18> am; // Alignment Mask
575 Bitfield<16> wp; // Write Protect
576 Bitfield<5> ne; // Numeric Error
577 Bitfield<4> et; // Extension Type
578 Bitfield<3> ts; // Task Switched
579 Bitfield<2> em; // Emulation
580 Bitfield<1> mp; // Monitor Coprocessor
581 Bitfield<0> pe; // Protection Enabled
584 // Page Fault Virtual Address
586 Bitfield<31, 0> legacy;
590 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
592 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
594 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
596 Bitfield<4> pcd; // Page-Level Cache Disable
597 Bitfield<3> pwt; // Page-Level Writethrough
601 Bitfield<10> osxmmexcpt; // Operating System Unmasked
603 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
604 Bitfield<8> pce; // Performance-Monitoring Counter Enable
605 Bitfield<7> pge; // Page-Global Enable
606 Bitfield<6> mce; // Machine Check Enable
607 Bitfield<5> pae; // Physical-Address Extension
608 Bitfield<4> pse; // Page Size Extensions
609 Bitfield<3> de; // Debugging Extensions
610 Bitfield<2> tsd; // Time Stamp Disable
611 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
612 Bitfield<0> vme; // Virtual-8086 Mode Extensions
616 Bitfield<3, 0> tpr; // Task Priority Register
641 Bitfield<17, 16> rw0;
642 Bitfield<19, 18> len0;
643 Bitfield<21, 20> rw1;
644 Bitfield<23, 22> len1;
645 Bitfield<25, 24> rw2;
646 Bitfield<27, 26> len2;
647 Bitfield<29, 28> rw3;
648 Bitfield<31, 30> len3;
653 Bitfield<7, 0> vcnt; // Variable-Range Register Count
654 Bitfield<8> fix; // Fixed-Range Registers
655 Bitfield<10> wc; // Write-Combining
659 * SYSENTER configuration registers
661 BitUnion64(SysenterCS)
662 Bitfield<15, 0> targetCS;
663 EndBitUnion(SysenterCS)
665 BitUnion64(SysenterESP)
666 Bitfield<31, 0> targetESP;
667 EndBitUnion(SysenterESP)
669 BitUnion64(SysenterEIP)
670 Bitfield<31, 0> targetEIP;
671 EndBitUnion(SysenterEIP)
674 * Global machine check registers
677 Bitfield<7, 0> count; // Number of error reporting register banks
678 Bitfield<8> MCGCP; // MCG_CTL register present.
681 BitUnion64(McgStatus)
682 Bitfield<0> ripv; // Restart-IP valid
683 Bitfield<1> eipv; // Error-IP valid
684 Bitfield<2> mcip; // Machine check in-progress
685 EndBitUnion(McgStatus)
687 BitUnion64(DebugCtlMsr)
688 Bitfield<0> lbr; // Last-branch record
689 Bitfield<1> btf; // Branch single step
690 Bitfield<2> pb0; // Performance monitoring pin control 0
691 Bitfield<3> pb1; // Performance monitoring pin control 1
692 Bitfield<4> pb2; // Performance monitoring pin control 2
693 Bitfield<5> pb3; // Performance monitoring pin control 3
694 /*uint64_t pb(int index)
696 return bits(__data, index + 2);
698 EndBitUnion(DebugCtlMsr)
700 BitUnion64(MtrrPhysBase)
701 Bitfield<7, 0> type; // Default memory type
702 Bitfield<51, 12> physbase; // Range physical base address
703 EndBitUnion(MtrrPhysBase)
705 BitUnion64(MtrrPhysMask)
706 Bitfield<11> valid; // MTRR pair enable
707 Bitfield<51, 12> physmask; // Range physical mask
708 EndBitUnion(MtrrPhysMask)
710 BitUnion64(MtrrFixed)
711 /*uint64_t type(int index)
713 return bits(__data, index * 8 + 7, index * 8);
715 EndBitUnion(MtrrFixed)
718 /*uint64_t pa(int index)
720 return bits(__data, index * 8 + 2, index * 8);
724 BitUnion64(MtrrDefType)
725 Bitfield<7, 0> type; // Default type
726 Bitfield<10> fe; // Fixed range enable
727 Bitfield<11> e; // MTRR enable
728 EndBitUnion(MtrrDefType)
734 Bitfield<15,0> mcaErrorCode;
735 Bitfield<31,16> modelSpecificCode;
736 Bitfield<56,32> otherInfo;
737 Bitfield<57> pcc; // Processor-context corrupt
738 Bitfield<58> addrv; // Error-address register valid
739 Bitfield<59> miscv; // Miscellaneous-error register valid
740 Bitfield<60> en; // Error condition enabled
741 Bitfield<61> uc; // Uncorrected error
742 Bitfield<62> over; // Status register overflow
743 Bitfield<63> val; // Valid
744 EndBitUnion(McStatus)
747 /*uint64_t en(int index)
749 return bits(__data, index);
753 // Extended feature enable register
755 Bitfield<0> sce; // System call extensions
756 Bitfield<8> lme; // Long mode enable
757 Bitfield<10> lma; // Long mode active
758 Bitfield<11> nxe; // No-execute enable
759 Bitfield<12> svme; // Secure virtual machine enable
760 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
764 Bitfield<31,0> targetEip;
765 Bitfield<47,32> syscallCsAndSs;
766 Bitfield<63,48> sysretCsAndSs;
773 BitUnion64(PerfEvtSel)
774 Bitfield<7,0> eventMask;
775 Bitfield<15,8> unitMask;
776 Bitfield<16> usr; // User mode
777 Bitfield<17> os; // Operating-system mode
778 Bitfield<18> e; // Edge detect
779 Bitfield<19> pc; // Pin control
780 Bitfield<20> intEn; // Interrupt enable
781 Bitfield<22> en; // Counter enable
782 Bitfield<23> inv; // Invert mask
783 Bitfield<31,24> counterMask;
784 EndBitUnion(PerfEvtSel)
787 Bitfield<18> mfde; // MtrrFixDramEn
788 Bitfield<19> mfdm; // MtrrFixDramModEn
789 Bitfield<20> mvdm; // MtrrVarDramEn
790 Bitfield<21> tom2; // MtrrTom2En
794 Bitfield<3> wr; // WrMem Enable
795 Bitfield<4> rd; // RdMem Enable
796 Bitfield<51,12> physbase; // Range physical base address
797 EndBitUnion(IorrBase)
800 Bitfield<11> v; // I/O register pair enable (valid)
801 Bitfield<51,12> physmask; // Range physical mask
802 EndBitUnion(IorrMask)
805 Bitfield<51,23> physAddr; // Top of memory physical address
816 EndBitUnion(IgnneMsr)
818 BitUnion64(SmmCtlMsr)
821 Bitfield<2> smiCycle;
823 Bitfield<4> rsmCycle;
824 EndBitUnion(SmmCtlMsr)
829 BitUnion64(SegSelector)
830 // The following bitfield is not defined in the ISA, but it's useful
831 // when checking selectors in larger data types to make sure they
833 Bitfield<63, 3> esi; // Extended selector
834 Bitfield<15, 3> si; // Selector Index
835 Bitfield<2> ti; // Table Indicator
836 Bitfield<1, 0> rpl; // Requestor Privilege Level
837 EndBitUnion(SegSelector)
840 * Segment Descriptors
843 BitUnion64(SegDescriptor)
844 Bitfield<63, 56> baseHigh;
845 Bitfield<39, 16> baseLow;
846 Bitfield<55> g; // Granularity
847 Bitfield<54> d; // Default Operand Size
848 Bitfield<54> b; // Default Operand Size
849 Bitfield<53> l; // Long Attribute Bit
850 Bitfield<52> avl; // Available To Software
851 Bitfield<51, 48> limitHigh;
852 Bitfield<15, 0> limitLow;
853 Bitfield<47> p; // Present
854 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
855 Bitfield<44> s; // System
856 SubBitUnion(type, 43, 40)
857 // Specifies whether this descriptor is for code or data.
858 Bitfield<43> codeOrData;
860 // These bit fields are for code segments
861 Bitfield<42> c; // Conforming
862 Bitfield<41> r; // Readable
864 // These bit fields are for data segments
865 Bitfield<42> e; // Expand-Down
866 Bitfield<41> w; // Writable
868 // This is used for both code and data segments.
869 Bitfield<40> a; // Accessed
871 EndBitUnion(SegDescriptor)
875 Bitfield<2> unusable;
876 Bitfield<3> defaultSize;
877 Bitfield<4> longMode;
879 Bitfield<6> granularity;
881 Bitfield<11, 8> type;
882 Bitfield<12> writable;
883 Bitfield<13> readable;
884 Bitfield<14> expandDown;
888 BitUnion64(GateDescriptor)
889 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
890 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
891 Bitfield<31, 16> selector; // Target Code-Segment Selector
892 Bitfield<47> p; // Present
893 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
894 Bitfield<43, 40> type;
895 Bitfield<36, 32> count; // Parameter Count
896 EndBitUnion(GateDescriptor)
899 * Descriptor-Table Registers
918 * Local APIC Base Register
920 BitUnion64(LocalApicBase)
921 Bitfield<51, 12> base;
924 EndBitUnion(LocalApicBase)
927 #endif // __ARCH_X86_INTREGS_HH__