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58 #ifndef __ARCH_X86_MISCREGS_HH__
59 #define __ARCH_X86_MISCREGS_HH__
61 #include "arch/x86/x86_traits.hh"
62 #include "base/bitunion.hh"
64 //These get defined in some system headers (at least termbits.h). That confuses
65 //things here significantly.
87 // Most of these are invalid.
89 MISCREG_CR0 = MISCREG_CR_BASE,
107 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
108 MISCREG_DR0 = MISCREG_DR_BASE,
118 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
121 * Model Specific Registers
123 // Time stamp counter
129 MISCREG_SYSENTER_ESP,
130 MISCREG_SYSENTER_EIP,
136 MISCREG_DEBUG_CTL_MSR,
138 MISCREG_LAST_BRANCH_FROM_IP,
139 MISCREG_LAST_BRANCH_TO_IP,
140 MISCREG_LAST_EXCEPTION_FROM_IP,
141 MISCREG_LAST_EXCEPTION_TO_IP,
143 MISCREG_MTRR_PHYS_BASE_BASE,
144 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
145 MISCREG_MTRR_PHYS_BASE_1,
146 MISCREG_MTRR_PHYS_BASE_2,
147 MISCREG_MTRR_PHYS_BASE_3,
148 MISCREG_MTRR_PHYS_BASE_4,
149 MISCREG_MTRR_PHYS_BASE_5,
150 MISCREG_MTRR_PHYS_BASE_6,
151 MISCREG_MTRR_PHYS_BASE_7,
153 MISCREG_MTRR_PHYS_MASK_BASE,
154 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
155 MISCREG_MTRR_PHYS_MASK_1,
156 MISCREG_MTRR_PHYS_MASK_2,
157 MISCREG_MTRR_PHYS_MASK_3,
158 MISCREG_MTRR_PHYS_MASK_4,
159 MISCREG_MTRR_PHYS_MASK_5,
160 MISCREG_MTRR_PHYS_MASK_6,
161 MISCREG_MTRR_PHYS_MASK_7,
163 MISCREG_MTRR_FIX_64K_00000,
164 MISCREG_MTRR_FIX_16K_80000,
165 MISCREG_MTRR_FIX_16K_A0000,
166 MISCREG_MTRR_FIX_4K_C0000,
167 MISCREG_MTRR_FIX_4k_C8000,
168 MISCREG_MTRR_FIX_4K_D0000,
169 MISCREG_MTRR_FIX_4K_D8000,
170 MISCREG_MTRR_FIX_4K_E0000,
171 MISCREG_MTRR_FIX_4K_E8000,
172 MISCREG_MTRR_FIX_4K_F0000,
173 MISCREG_MTRR_FIX_4K_F8000,
180 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
186 MISCREG_MC_STATUS_BASE,
187 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
193 MISCREG_MC_ADDR_BASE,
194 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
200 MISCREG_MC_MISC_BASE,
201 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
207 // Extended feature enable register
216 MISCREG_KERNEL_GS_BASE,
220 MISCREG_PERF_EVT_SEL_BASE,
221 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
222 MISCREG_PERF_EVT_SEL1,
223 MISCREG_PERF_EVT_SEL2,
224 MISCREG_PERF_EVT_SEL3,
226 MISCREG_PERF_EVT_CTR_BASE,
227 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
228 MISCREG_PERF_EVT_CTR1,
229 MISCREG_PERF_EVT_CTR2,
230 MISCREG_PERF_EVT_CTR3,
234 MISCREG_IORR_BASE_BASE,
235 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
238 MISCREG_IORR_MASK_BASE,
239 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
254 MISCREG_SEG_SEL_BASE,
255 MISCREG_ES = MISCREG_SEG_SEL_BASE,
262 // Hidden segment base field
263 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
264 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
271 // Hidden segment limit field
272 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
273 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
280 // Hidden segment limit attributes
281 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
282 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
289 // System segment selectors
290 MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
291 MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
294 // Hidden system segment base field
295 MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
296 MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
301 // Hidden system segment limit field
302 MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
303 MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
308 // Hidden system segment attribute field
309 MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
310 MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
313 // Floating point control registers
314 MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments,
316 //XXX Add "Model-Specific Registers"
321 static inline MiscRegIndex
322 MISCREG_CR(int index)
324 return (MiscRegIndex)(MISCREG_CR_BASE + index);
327 static inline MiscRegIndex
328 MISCREG_DR(int index)
330 return (MiscRegIndex)(MISCREG_DR_BASE + index);
333 static inline MiscRegIndex
334 MISCREG_MTRR_PHYS_BASE(int index)
336 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
339 static inline MiscRegIndex
340 MISCREG_MTRR_PHYS_MASK(int index)
342 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
345 static inline MiscRegIndex
346 MISCREG_MC_CTL(int index)
348 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
351 static inline MiscRegIndex
352 MISCREG_MC_STATUS(int index)
354 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
357 static inline MiscRegIndex
358 MISCREG_MC_ADDR(int index)
360 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
363 static inline MiscRegIndex
364 MISCREG_MC_MISC(int index)
366 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
369 static inline MiscRegIndex
370 MISCREG_PERF_EVT_SEL(int index)
372 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
375 static inline MiscRegIndex
376 MISCREG_PERF_EVT_CTR(int index)
378 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
381 static inline MiscRegIndex
382 MISCREG_IORR_BASE(int index)
384 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
387 static inline MiscRegIndex
388 MISCREG_IORR_MASK(int index)
390 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
393 static inline MiscRegIndex
394 MISCREG_SEG_SEL(int index)
396 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
399 static inline MiscRegIndex
400 MISCREG_SEG_BASE(int index)
402 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
405 static inline MiscRegIndex
406 MISCREG_SEG_LIMIT(int index)
408 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
411 static inline MiscRegIndex
412 MISCREG_SEG_ATTR(int index)
414 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
417 static inline MiscRegIndex
418 MISCREG_SYSSEG_SEL(int index)
420 return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
423 static inline MiscRegIndex
424 MISCREG_SYSSEG_BASE(int index)
426 return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
429 static inline MiscRegIndex
430 MISCREG_SYSSEG_LIMIT(int index)
432 return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
435 static inline MiscRegIndex
436 MISCREG_SYSSEG_ATTR(int index)
438 return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
442 * A type to describe the condition code bits of the RFLAGS register,
443 * plus two flags, EZF and ECF, which are only visible to microcode.
445 BitUnion64(CCFlagBits)
454 EndBitUnion(CCFlagBits)
460 Bitfield<21> id; // ID Flag
461 Bitfield<20> vip; // Virtual Interrupt Pending
462 Bitfield<19> vif; // Virtual Interrupt Flag
463 Bitfield<18> ac; // Alignment Check
464 Bitfield<17> vm; // Virtual-8086 Mode
465 Bitfield<16> rf; // Resume Flag
466 Bitfield<14> nt; // Nested Task
467 Bitfield<13, 12> iopl; // I/O Privilege Level
468 Bitfield<11> of; // Overflow Flag
469 Bitfield<10> df; // Direction Flag
470 Bitfield<9> intf; // Interrupt Flag
471 Bitfield<8> tf; // Trap Flag
472 Bitfield<7> sf; // Sign Flag
473 Bitfield<6> zf; // Zero Flag
474 Bitfield<4> af; // Auxiliary Flag
475 Bitfield<2> pf; // Parity Flag
476 Bitfield<0> cf; // Carry Flag
483 Bitfield<31> pg; // Paging
484 Bitfield<30> cd; // Cache Disable
485 Bitfield<29> nw; // Not Writethrough
486 Bitfield<18> am; // Alignment Mask
487 Bitfield<16> wp; // Write Protect
488 Bitfield<5> ne; // Numeric Error
489 Bitfield<4> et; // Extension Type
490 Bitfield<3> ts; // Task Switched
491 Bitfield<2> em; // Emulation
492 Bitfield<1> mp; // Monitor Coprocessor
493 Bitfield<0> pe; // Protection Enabled
496 // Page Fault Virtual Address
498 Bitfield<31, 0> legacy;
502 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
504 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
506 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
508 Bitfield<4> pcd; // Page-Level Cache Disable
509 Bitfield<3> pwt; // Page-Level Writethrough
513 Bitfield<10> osxmmexcpt; // Operating System Unmasked
515 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
516 Bitfield<8> pce; // Performance-Monitoring Counter Enable
517 Bitfield<7> pge; // Page-Global Enable
518 Bitfield<6> mce; // Machine Check Enable
519 Bitfield<5> pae; // Physical-Address Extension
520 Bitfield<4> pse; // Page Size Extensions
521 Bitfield<3> de; // Debugging Extensions
522 Bitfield<2> tsd; // Time Stamp Disable
523 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
524 Bitfield<0> vme; // Virtual-8086 Mode Extensions
528 Bitfield<3, 0> tpr; // Task Priority Register
533 Bitfield<7, 0> vcnt; // Variable-Range Register Count
534 Bitfield<8> fix; // Fixed-Range Registers
535 Bitfield<10> wc; // Write-Combining
539 * SYSENTER configuration registers
541 BitUnion64(SysenterCS)
542 Bitfield<15, 0> targetCS;
543 EndBitUnion(SysenterCS)
545 BitUnion64(SysenterESP)
546 Bitfield<31, 0> targetESP;
547 EndBitUnion(SysenterESP)
549 BitUnion64(SysenterEIP)
550 Bitfield<31, 0> targetEIP;
551 EndBitUnion(SysenterEIP)
554 * Global machine check registers
557 Bitfield<7, 0> count; // Number of error reporting register banks
558 Bitfield<8> MCGCP; // MCG_CTL register present.
561 BitUnion64(McgStatus)
562 Bitfield<0> ripv; // Restart-IP valid
563 Bitfield<1> eipv; // Error-IP valid
564 Bitfield<2> mcip; // Machine check in-progress
565 EndBitUnion(McgStatus)
567 BitUnion64(DebugCtlMsr)
568 Bitfield<0> lbr; // Last-branch record
569 Bitfield<1> btf; // Branch single step
570 Bitfield<2> pb0; // Performance monitoring pin control 0
571 Bitfield<3> pb1; // Performance monitoring pin control 1
572 Bitfield<4> pb2; // Performance monitoring pin control 2
573 Bitfield<5> pb3; // Performance monitoring pin control 3
574 /*uint64_t pb(int index)
576 return bits(__data, index + 2);
578 EndBitUnion(DebugCtlMsr)
580 BitUnion64(MtrrPhysBase)
581 Bitfield<7, 0> type; // Default memory type
582 Bitfield<51, 12> physbase; // Range physical base address
583 EndBitUnion(MtrrPhysBase)
585 BitUnion64(MtrrPhysMask)
586 Bitfield<11> valid; // MTRR pair enable
587 Bitfield<51, 12> physmask; // Range physical mask
588 EndBitUnion(MtrrPhysMask)
590 BitUnion64(MtrrFixed)
591 /*uint64_t type(int index)
593 return bits(__data, index * 8 + 7, index * 8);
595 EndBitUnion(MtrrFixed)
598 /*uint64_t pa(int index)
600 return bits(__data, index * 8 + 2, index * 8);
604 BitUnion64(MtrrDefType)
605 Bitfield<7, 0> type; // Default type
606 Bitfield<10> fe; // Fixed range enable
607 Bitfield<11> e; // MTRR enable
608 EndBitUnion(MtrrDefType)
614 Bitfield<15,0> mcaErrorCode;
615 Bitfield<31,16> modelSpecificCode;
616 Bitfield<56,32> otherInfo;
617 Bitfield<57> pcc; // Processor-context corrupt
618 Bitfield<58> addrv; // Error-address register valid
619 Bitfield<59> miscv; // Miscellaneous-error register valid
620 Bitfield<60> en; // Error condition enabled
621 Bitfield<61> uc; // Uncorrected error
622 Bitfield<62> over; // Status register overflow
623 Bitfield<63> val; // Valid
624 EndBitUnion(McStatus)
627 /*uint64_t en(int index)
629 return bits(__data, index);
633 // Extended feature enable register
635 Bitfield<0> sce; // System call extensions
636 Bitfield<8> lme; // Long mode enable
637 Bitfield<10> lma; // Long mode active
638 Bitfield<11> nxe; // No-execute enable
639 Bitfield<12> svme; // Secure virtual machine enable
640 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
644 Bitfield<31,0> targetEip;
645 Bitfield<47,32> syscallCsAndSs;
646 Bitfield<63,48> sysretCsAndSs;
653 BitUnion64(PerfEvtSel)
654 Bitfield<7,0> eventMask;
655 Bitfield<15,8> unitMask;
656 Bitfield<16> usr; // User mode
657 Bitfield<17> os; // Operating-system mode
658 Bitfield<18> e; // Edge detect
659 Bitfield<19> pc; // Pin control
660 Bitfield<20> intEn; // Interrupt enable
661 Bitfield<22> en; // Counter enable
662 Bitfield<23> inv; // Invert mask
663 Bitfield<31,24> counterMask;
664 EndBitUnion(PerfEvtSel)
667 Bitfield<18> mfde; // MtrrFixDramEn
668 Bitfield<19> mfdm; // MtrrFixDramModEn
669 Bitfield<20> mvdm; // MtrrVarDramEn
670 Bitfield<21> tom2; // MtrrTom2En
674 Bitfield<3> wr; // WrMem Enable
675 Bitfield<4> rd; // RdMem Enable
676 Bitfield<51,12> physbase; // Range physical base address
677 EndBitUnion(IorrBase)
680 Bitfield<11> v; // I/O register pair enable (valid)
681 Bitfield<51,12> physmask; // Range physical mask
682 EndBitUnion(IorrMask)
685 Bitfield<51,23> physAddr; // Top of memory physical address
696 EndBitUnion(IgnneMsr)
698 BitUnion64(SmmCtlMsr)
701 Bitfield<2> smiCycle;
703 Bitfield<4> rsmCycle;
704 EndBitUnion(SmmCtlMsr)
709 BitUnion64(SegSelector)
710 Bitfield<15, 3> si; // Selector Index
711 Bitfield<2> ti; // Table Indicator
712 Bitfield<1, 0> rpl; // Requestor Privilege Level
713 EndBitUnion(SegSelector)
716 * Segment Descriptors
719 BitUnion64(SegDescriptor)
720 Bitfield<63, 56> baseHigh;
721 Bitfield<39, 16> baseLow;
722 Bitfield<55> g; // Granularity
723 Bitfield<54> d; // Default Operand Size
724 Bitfield<54> b; // Default Operand Size
725 Bitfield<53> l; // Long Attribute Bit
726 Bitfield<52> avl; // Available To Software
727 Bitfield<51, 48> limitHigh;
728 Bitfield<15, 0> limitLow;
729 Bitfield<47> p; // Present
730 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
731 Bitfield<44> s; // System
732 SubBitUnion(type, 43, 40)
733 // Specifies whether this descriptor is for code or data.
734 Bitfield<43> codeOrData;
736 // These bit fields are for code segments
737 Bitfield<42> c; // Conforming
738 Bitfield<41> r; // Readable
740 // These bit fields are for data segments
741 Bitfield<42> e; // Expand-Down
742 Bitfield<41> w; // Writable
744 // This is used for both code and data segments.
745 Bitfield<40> a; // Accessed
747 EndBitUnion(SegDescriptor)
750 Bitfield<0> writable;
751 Bitfield<1> readable;
752 Bitfield<2> expandDown;
754 Bitfield<5> defaultSize;
755 Bitfield<6> longMode;
758 BitUnion64(GateDescriptor)
759 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
760 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
761 Bitfield<31, 16> selector; // Target Code-Segment Selector
762 Bitfield<47> p; // Present
763 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
764 Bitfield<43, 40> type;
765 Bitfield<36, 32> count; // Parameter Count
766 EndBitUnion(GateDescriptor)
769 * Descriptor-Table Registers
787 #endif // __ARCH_X86_INTREGS_HH__