src/arch/x86/nativetrace.cc

   1 /*
   2  * Copyright (c) 2007-2009 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #include "arch/x86/isa_traits.hh"
  32 #include "arch/x86/nativetrace.hh"
  33 #include "arch/x86/regs/float.hh"
  34 #include "arch/x86/regs/int.hh"
  35 #include "cpu/thread_context.hh"
  36 #include "params/X86NativeTrace.hh"
  37
  38 namespace Trace {
  39
  40 void
  41 X86NativeTrace::ThreadState::update(NativeTrace *parent)
  42 {
  43     parent->read(this, sizeof(*this));
  44     rax = X86ISA::gtoh(rax);
  45     rcx = X86ISA::gtoh(rcx);
  46     rdx = X86ISA::gtoh(rdx);
  47     rbx = X86ISA::gtoh(rbx);
  48     rsp = X86ISA::gtoh(rsp);
  49     rbp = X86ISA::gtoh(rbp);
  50     rsi = X86ISA::gtoh(rsi);
  51     rdi = X86ISA::gtoh(rdi);
  52     r8 = X86ISA::gtoh(r8);
  53     r9 = X86ISA::gtoh(r9);
  54     r10 = X86ISA::gtoh(r10);
  55     r11 = X86ISA::gtoh(r11);
  56     r12 = X86ISA::gtoh(r12);
  57     r13 = X86ISA::gtoh(r13);
  58     r14 = X86ISA::gtoh(r14);
  59     r15 = X86ISA::gtoh(r15);
  60     rip = X86ISA::gtoh(rip);
  61     //This should be expanded if x87 registers are considered
  62     for (int i = 0; i < 8; i++)
  63         mmx[i] = X86ISA::gtoh(mmx[i]);
  64     for (int i = 0; i < 32; i++)
  65         xmm[i] = X86ISA::gtoh(xmm[i]);
  66 }
  67
  68 void
  69 X86NativeTrace::ThreadState::update(ThreadContext *tc)
  70 {
  71     rax = tc->readIntReg(X86ISA::INTREG_RAX);
  72     rcx = tc->readIntReg(X86ISA::INTREG_RCX);
  73     rdx = tc->readIntReg(X86ISA::INTREG_RDX);
  74     rbx = tc->readIntReg(X86ISA::INTREG_RBX);
  75     rsp = tc->readIntReg(X86ISA::INTREG_RSP);
  76     rbp = tc->readIntReg(X86ISA::INTREG_RBP);
  77     rsi = tc->readIntReg(X86ISA::INTREG_RSI);
  78     rdi = tc->readIntReg(X86ISA::INTREG_RDI);
  79     r8 = tc->readIntReg(X86ISA::INTREG_R8);
  80     r9 = tc->readIntReg(X86ISA::INTREG_R9);
  81     r10 = tc->readIntReg(X86ISA::INTREG_R10);
  82     r11 = tc->readIntReg(X86ISA::INTREG_R11);
  83     r12 = tc->readIntReg(X86ISA::INTREG_R12);
  84     r13 = tc->readIntReg(X86ISA::INTREG_R13);
  85     r14 = tc->readIntReg(X86ISA::INTREG_R14);
  86     r15 = tc->readIntReg(X86ISA::INTREG_R15);
  87     rip = tc->readNextPC();
  88     //This should be expanded if x87 registers are considered
  89     for (int i = 0; i < 8; i++)
  90         mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
  91     for (int i = 0; i < 32; i++)
  92         xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
  93 }
  94
  95
  96 X86NativeTrace::X86NativeTrace(const Params *p)
  97     : NativeTrace(p)
  98 {
  99     checkRcx = true;
 100     checkR11 = true;
 101 }
 102
 103 bool
 104 X86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
 105 {
 106     if(!checkRcx)
 107         checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
 108     if(checkRcx)
 109         return checkReg(name, mVal, nVal);
 110     return true;
 111 }
 112
 113 bool
 114 X86NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
 115 {
 116     if(!checkR11)
 117         checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
 118     if(checkR11)
 119         return checkReg(name, mVal, nVal);
 120     return true;
 121 }
 122
 123 bool
 124 X86NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
 125 {
 126     if (mXmmBuf[num * 2]     != nXmmBuf[num * 2] ||
 127         mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
 128         DPRINTF(ExecRegDelta,
 129                 "Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
 130                 num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
 131                      mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
 132         return false;
 133     }
 134     return true;
 135 }
 136
 137 void
 138 X86NativeTrace::check(NativeTraceRecord *record)
 139 {
 140     nState.update(this);
 141     mState.update(record->getThread());
 142
 143     if(record->getStaticInst()->isSyscall())
 144     {
 145         checkRcx = false;
 146         checkR11 = false;
 147         oldRcxVal = mState.rcx;
 148         oldRealRcxVal = nState.rcx;
 149         oldR11Val = mState.r11;
 150         oldRealR11Val = nState.r11;
 151     }
 152
 153     checkReg("rax", mState.rax, nState.rax);
 154     checkRcxReg("rcx", mState.rcx, nState.rcx);
 155     checkReg("rdx", mState.rdx, nState.rdx);
 156     checkReg("rbx", mState.rbx, nState.rbx);
 157     checkReg("rsp", mState.rsp, nState.rsp);
 158     checkReg("rbp", mState.rbp, nState.rbp);
 159     checkReg("rsi", mState.rsi, nState.rsi);
 160     checkReg("rdi", mState.rdi, nState.rdi);
 161     checkReg("r8",  mState.r8,  nState.r8);
 162     checkReg("r9",  mState.r9,  nState.r9);
 163     checkReg("r10", mState.r10, nState.r10);
 164     checkR11Reg("r11", mState.r11, nState.r11);
 165     checkReg("r12", mState.r12, nState.r12);
 166     checkReg("r13", mState.r13, nState.r13);
 167     checkReg("r14", mState.r14, nState.r14);
 168     checkReg("r15", mState.r15, nState.r15);
 169     checkReg("rip", mState.rip, nState.rip);
 170     checkXMM(0, mState.xmm, nState.xmm);
 171     checkXMM(1, mState.xmm, nState.xmm);
 172     checkXMM(2, mState.xmm, nState.xmm);
 173     checkXMM(3, mState.xmm, nState.xmm);
 174     checkXMM(4, mState.xmm, nState.xmm);
 175     checkXMM(5, mState.xmm, nState.xmm);
 176     checkXMM(6, mState.xmm, nState.xmm);
 177     checkXMM(7, mState.xmm, nState.xmm);
 178     checkXMM(8, mState.xmm, nState.xmm);
 179     checkXMM(9, mState.xmm, nState.xmm);
 180     checkXMM(10, mState.xmm, nState.xmm);
 181     checkXMM(11, mState.xmm, nState.xmm);
 182     checkXMM(12, mState.xmm, nState.xmm);
 183     checkXMM(13, mState.xmm, nState.xmm);
 184     checkXMM(14, mState.xmm, nState.xmm);
 185     checkXMM(15, mState.xmm, nState.xmm);
 186 }
 187
 188 } /* namespace Trace */
 189
 190 ////////////////////////////////////////////////////////////////////////
 191 //
 192 //  ExeTracer Simulation Object
 193 //
 194 Trace::X86NativeTrace *
 195 X86NativeTraceParams::create()
 196 {
 197     return new Trace::X86NativeTrace(this);
 198 };