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41 #ifndef __ARCH_X86_PAGETABLE_HH__
42 #define __ARCH_X86_PAGETABLE_HH__
48 #include "base/bitunion.hh"
49 #include "base/misc.hh"
50 #include "base/types.hh"
51 #include "base/trie.hh"
52 #include "cpu/thread_context.hh"
53 #include "arch/x86/system.hh"
54 #include "debug/MMU.hh"
63 typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
68 Bitfield<20, 12> longl1;
69 Bitfield<29, 21> longl2;
70 Bitfield<38, 30> longl3;
71 Bitfield<47, 39> longl4;
73 Bitfield<20, 12> pael1;
74 Bitfield<29, 21> pael2;
75 Bitfield<31, 30> pael3;
77 Bitfield<21, 12> norml1;
78 Bitfield<31, 22> norml2;
81 // Unfortunately, the placement of the base field in a page table entry is
82 // very erratic and would make a mess here. It might be moved here at some
83 // point in the future.
84 BitUnion64(PageTableEntry)
86 Bitfield<51, 12> base;
97 EndBitUnion(PageTableEntry)
102 // The base of the physical page.
105 // The beginning of the virtual page this entry maps.
107 // The size of the page this represents, in address bits.
110 // Read permission is always available, assuming it isn't blocked by
113 // Whether this page is accesible without being in supervisor mode.
115 // Whether to use write through or write back. M5 ignores this and
116 // lets the caches handle the writeback policy.
118 // Whether the page is cacheable or not.
120 // Whether or not to kick this page out on a write to CR3.
122 // A bit used to form an index into the PAT table.
124 // Whether or not memory on this page can be executed.
126 // A sequence number to keep track of LRU.
129 TlbEntryTrie::Handle trieHandle;
131 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr,
132 bool uncacheable, bool read_only);
136 updateVaddr(Addr new_vaddr)
146 // Return the page size in bytes
149 return (1 << logBytes);
152 void serialize(std::ostream &os);
153 void unserialize(Checkpoint *cp, const std::string §ion);
156 /** The size of each level of the page table expressed in base 2
159 const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9};
161 /* x86 specific PTE flags */
169 /** Page table operations specific to x86 ISA.
170 * Indended to be used as parameter of MultiLevelPageTable.
175 void setPTEFields(PageTableEntry& PTE, uint64_t flags = 0)
177 PTE.p = flags & PTE_NotPresent ? 0 : 1;
178 PTE.pcd = flags & PTE_Uncacheable ? 1 : 0;
179 PTE.w = flags & PTE_ReadOnly ? 0 : 1;
180 PTE.u = flags & PTE_Supervisor ? 0 : 1;
183 /** returns the physical memory address of the page table */
184 Addr getBasePtr(ThreadContext* tc)
186 CR3 cr3 = pageTablePhysAddr;
187 DPRINTF(MMU, "CR3: %d\n", cr3);
191 /** returns the page number out of a page table entry */
192 Addr getPnum(PageTableEntry PTE)
197 bool isUncacheable(const PageTableEntry PTE)
202 bool isReadOnly(PageTableEntry PTE)
207 /** sets the page number in a page table entry */
208 void setPnum(PageTableEntry& PTE, Addr paddr)
213 /** returns the offsets to index in every level of a page
214 * table, contained in a virtual address
216 std::vector<uint64_t> getOffsets(Addr vaddr)
218 X86ISA::VAddr addr(vaddr);
219 return {addr.longl1, addr.longl2, addr.longl3, addr.longl4};