src/arch/x86/pagetable.hh

   1 /*
   2  * Copyright (c) 2014 Advanced Micro Devices, Inc.
   3  * Copyright (c) 2007 The Hewlett-Packard Development Company
   4  * All rights reserved.
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions are
  17  * met: redistributions of source code must retain the above copyright
  18  * notice, this list of conditions and the following disclaimer;
  19  * redistributions in binary form must reproduce the above copyright
  20  * notice, this list of conditions and the following disclaimer in the
  21  * documentation and/or other materials provided with the distribution;
  22  * neither the name of the copyright holders nor the names of its
  23  * contributors may be used to endorse or promote products derived from
  24  * this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #ifndef __ARCH_X86_PAGETABLE_HH__
  40 #define __ARCH_X86_PAGETABLE_HH__
  41
  42 #include <iostream>
  43 #include <string>
  44 #include <vector>
  45
  46 #include "base/bitunion.hh"
  47 #include "base/types.hh"
  48 #include "base/trie.hh"
  49 #include "arch/x86/system.hh"
  50 #include "debug/MMU.hh"
  51
  52 class Checkpoint;
  53 class ThreadContext;
  54
  55 namespace X86ISA
  56 {
  57     struct TlbEntry;
  58 }
  59
  60 typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
  61
  62 namespace X86ISA
  63 {
  64     struct TlbEntry : public Serializable
  65     {
  66         // The base of the physical page.
  67         Addr paddr;
  68
  69         // The beginning of the virtual page this entry maps.
  70         Addr vaddr;
  71         // The size of the page this represents, in address bits.
  72         unsigned logBytes;
  73
  74         // Read permission is always available, assuming it isn't blocked by
  75         // other mechanisms.
  76         bool writable;
  77         // Whether this page is accesible without being in supervisor mode.
  78         bool user;
  79         // Whether to use write through or write back. M5 ignores this and
  80         // lets the caches handle the writeback policy.
  81         //bool pwt;
  82         // Whether the page is cacheable or not.
  83         bool uncacheable;
  84         // Whether or not to kick this page out on a write to CR3.
  85         bool global;
  86         // A bit used to form an index into the PAT table.
  87         bool patBit;
  88         // Whether or not memory on this page can be executed.
  89         bool noExec;
  90         // A sequence number to keep track of LRU.
  91         uint64_t lruSeq;
  92
  93         TlbEntryTrie::Handle trieHandle;
  94
  95         TlbEntry(Addr asn, Addr _vaddr, Addr _paddr,
  96                  bool uncacheable, bool read_only);
  97         TlbEntry();
  98
  99         void
 100         updateVaddr(Addr new_vaddr)
 101         {
 102             vaddr = new_vaddr;
 103         }
 104
 105         Addr pageStart()
 106         {
 107             return paddr;
 108         }
 109
 110         // Return the page size in bytes
 111         int size()
 112         {
 113             return (1 << logBytes);
 114         }
 115
 116         void serialize(CheckpointOut &cp) const override;
 117         void unserialize(CheckpointIn &cp) override;
 118     };
 119
 120
 121     BitUnion64(VAddr)
 122         Bitfield<20, 12> longl1;
 123         Bitfield<29, 21> longl2;
 124         Bitfield<38, 30> longl3;
 125         Bitfield<47, 39> longl4;
 126
 127         Bitfield<20, 12> pael1;
 128         Bitfield<29, 21> pael2;
 129         Bitfield<31, 30> pael3;
 130
 131         Bitfield<21, 12> norml1;
 132         Bitfield<31, 22> norml2;
 133     EndBitUnion(VAddr)
 134
 135     // Unfortunately, the placement of the base field in a page table entry is
 136     // very erratic and would make a mess here. It might be moved here at some
 137     // point in the future.
 138     BitUnion64(PageTableEntry)
 139         Bitfield<63> nx;
 140         Bitfield<51, 12> base;
 141         Bitfield<11, 9> avl;
 142         Bitfield<8> g;
 143         Bitfield<7> ps;
 144         Bitfield<6> d;
 145         Bitfield<5> a;
 146         Bitfield<4> pcd;
 147         Bitfield<3> pwt;
 148         Bitfield<2> u;
 149         Bitfield<1> w;
 150         Bitfield<0> p;
 151     EndBitUnion(PageTableEntry)
 152
 153     template <int first, int last>
 154     class LongModePTE
 155     {
 156       public:
 157         Addr paddr() { return pte.base << PageShift; }
 158         void paddr(Addr addr) { pte.base = addr >> PageShift; }
 159
 160         bool present() { return pte.p; }
 161         void present(bool p) { pte.p = p ? 1 : 0; }
 162
 163         bool uncacheable() { return pte.pcd; }
 164         void uncacheable(bool u) { pte.pcd = u ? 1 : 0; }
 165
 166         bool readonly() { return !pte.w; }
 167         void readonly(bool r) { pte.w = r ? 0 : 1; }
 168
 169         void
 170         read(PortProxy &p, Addr table, Addr vaddr)
 171         {
 172             entryAddr = table;
 173             entryAddr += bits(vaddr, first, last) * sizeof(PageTableEntry);
 174             pte = p.read<PageTableEntry>(entryAddr);
 175         }
 176
 177         void
 178         reset(Addr _paddr, bool _present=true,
 179               bool _uncacheable=false, bool _readonly=false)
 180         {
 181             pte = 0;
 182             pte.u = 1;
 183             paddr(_paddr);
 184             present(_present);
 185             uncacheable(_uncacheable);
 186             readonly(_readonly);
 187         };
 188
 189         void write(PortProxy &p) { p.write(entryAddr, pte); }
 190
 191         static int
 192         tableSize()
 193         {
 194             return 1 << ((first - last) + 4 - PageShift);
 195         }
 196
 197       protected:
 198         PageTableEntry pte;
 199         Addr entryAddr;
 200     };
 201 }
 202
 203 #endif