src/arch/x86/pagetable.hh

   1 /*
   2  * Copyright (c) 2014 Advanced Micro Devices, Inc.
   3  * Copyright (c) 2007 The Hewlett-Packard Development Company
   4  * All rights reserved.
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions are
  17  * met: redistributions of source code must retain the above copyright
  18  * notice, this list of conditions and the following disclaimer;
  19  * redistributions in binary form must reproduce the above copyright
  20  * notice, this list of conditions and the following disclaimer in the
  21  * documentation and/or other materials provided with the distribution;
  22  * neither the name of the copyright holders nor the names of its
  23  * contributors may be used to endorse or promote products derived from
  24  * this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  * Authors: Gabe Black
  39  */
  40
  41 #ifndef __ARCH_X86_PAGETABLE_HH__
  42 #define __ARCH_X86_PAGETABLE_HH__
  43
  44 #include <iostream>
  45 #include <string>
  46 #include <vector>
  47
  48 #include "base/bitunion.hh"
  49 #include "base/misc.hh"
  50 #include "base/types.hh"
  51 #include "base/trie.hh"
  52 #include "cpu/thread_context.hh"
  53 #include "arch/x86/system.hh"
  54 #include "debug/MMU.hh"
  55
  56 class Checkpoint;
  57
  58 namespace X86ISA
  59 {
  60     struct TlbEntry;
  61 }
  62
  63 typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
  64
  65 namespace X86ISA
  66 {
  67     BitUnion64(VAddr)
  68         Bitfield<20, 12> longl1;
  69         Bitfield<29, 21> longl2;
  70         Bitfield<38, 30> longl3;
  71         Bitfield<47, 39> longl4;
  72
  73         Bitfield<20, 12> pael1;
  74         Bitfield<29, 21> pael2;
  75         Bitfield<31, 30> pael3;
  76
  77         Bitfield<21, 12> norml1;
  78         Bitfield<31, 22> norml2;
  79     EndBitUnion(VAddr)
  80
  81     // Unfortunately, the placement of the base field in a page table entry is
  82     // very erratic and would make a mess here. It might be moved here at some
  83     // point in the future.
  84     BitUnion64(PageTableEntry)
  85         Bitfield<63> nx;
  86         Bitfield<51, 12> base;
  87         Bitfield<11, 9> avl;
  88         Bitfield<8> g;
  89         Bitfield<7> ps;
  90         Bitfield<6> d;
  91         Bitfield<5> a;
  92         Bitfield<4> pcd;
  93         Bitfield<3> pwt;
  94         Bitfield<2> u;
  95         Bitfield<1> w;
  96         Bitfield<0> p;
  97     EndBitUnion(PageTableEntry)
  98
  99
 100     struct TlbEntry
 101     {
 102         // The base of the physical page.
 103         Addr paddr;
 104
 105         // The beginning of the virtual page this entry maps.
 106         Addr vaddr;
 107         // The size of the page this represents, in address bits.
 108         unsigned logBytes;
 109
 110         // Read permission is always available, assuming it isn't blocked by
 111         // other mechanisms.
 112         bool writable;
 113         // Whether this page is accesible without being in supervisor mode.
 114         bool user;
 115         // Whether to use write through or write back. M5 ignores this and
 116         // lets the caches handle the writeback policy.
 117         //bool pwt;
 118         // Whether the page is cacheable or not.
 119         bool uncacheable;
 120         // Whether or not to kick this page out on a write to CR3.
 121         bool global;
 122         // A bit used to form an index into the PAT table.
 123         bool patBit;
 124         // Whether or not memory on this page can be executed.
 125         bool noExec;
 126         // A sequence number to keep track of LRU.
 127         uint64_t lruSeq;
 128
 129         TlbEntryTrie::Handle trieHandle;
 130
 131         TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
 132         TlbEntry() {}
 133
 134         void
 135         updateVaddr(Addr new_vaddr)
 136         {
 137             vaddr = new_vaddr;
 138         }
 139
 140         Addr pageStart()
 141         {
 142             return paddr;
 143         }
 144
 145         // Return the page size in bytes
 146         int size()
 147         {
 148             return (1 << logBytes);
 149         }
 150
 151         void serialize(std::ostream &os);
 152         void unserialize(Checkpoint *cp, const std::string &section);
 153     };
 154
 155     /** The size of each level of the page table expressed in base 2
 156      * logarithmic values
 157      */
 158     const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9};
 159
 160     enum PTEField{
 161         PTE_NotPresent = 0,
 162         PTE_Present,
 163         PTE_ReadOnly = 0,
 164         PTE_ReadWrite,
 165         PTE_Supervisor = 0,
 166         PTE_UserSupervisor,
 167     };
 168
 169     /** Page table operations specific to x86 ISA.
 170      * Indended to be used as parameter of MultiLevelPageTable.
 171      */
 172     class PageTableOps
 173     {
 174       public:
 175         void setPTEFields(PageTableEntry& PTE,
 176                           uint64_t present = PTE_Present,
 177                           uint64_t read_write = PTE_ReadWrite,
 178                           uint64_t user_supervisor = PTE_UserSupervisor)
 179         {
 180             PTE.p = present;
 181             PTE.w = read_write;
 182             PTE.u = user_supervisor;// both user and supervisor access allowed
 183         }
 184
 185         /** returns the physical memory address of the page table */
 186         Addr getBasePtr(ThreadContext* tc)
 187         {
 188             CR3 cr3 = pageTablePhysAddr;
 189             DPRINTF(MMU, "CR3: %d\n", cr3);
 190             return cr3.longPdtb;
 191         }
 192
 193         /** returns the page number out of a page table entry */
 194         Addr getPnum(PageTableEntry PTE)
 195         {
 196             return PTE.base;
 197         }
 198
 199         /** sets the page number in a page table entry */
 200         void setPnum(PageTableEntry& PTE, Addr paddr)
 201         {
 202             PTE.base = paddr;
 203         }
 204
 205         /** returns the offsets to index in every level of a page
 206          * table, contained in a virtual address
 207          */
 208         std::vector<uint64_t> getOffsets(Addr vaddr)
 209         {
 210             X86ISA::VAddr addr(vaddr);
 211             return {addr.longl1, addr.longl2, addr.longl3, addr.longl4};
 212         }
 213     };
 214
 215 }
 216
 217 #endif