X86: Fix the expected size of the immediate offset in MOV_MI.
[gem5.git] / src / arch / x86 / pagetable.hh
1 /*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
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17 *
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23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
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35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
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39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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55 * Authors: Gabe Black
56 */
57
58 #ifndef __ARCH_X86_PAGETABLE_HH__
59 #define __ARCH_X86_PAGETABLE_HH__
60
61 #include <iostream>
62 #include <string>
63
64 #include "base/bitunion.hh"
65 #include "base/misc.hh"
66 #include "base/types.hh"
67
68 class Checkpoint;
69
70 namespace X86ISA
71 {
72 BitUnion64(VAddr)
73 Bitfield<20, 12> longl1;
74 Bitfield<29, 21> longl2;
75 Bitfield<38, 30> longl3;
76 Bitfield<47, 39> longl4;
77
78 Bitfield<20, 12> pael1;
79 Bitfield<29, 21> pael2;
80 Bitfield<31, 30> pael3;
81
82 Bitfield<21, 12> norml1;
83 Bitfield<31, 22> norml2;
84 EndBitUnion(VAddr)
85
86 struct TlbEntry
87 {
88 // The base of the physical page.
89 Addr paddr;
90
91 // The beginning of the virtual page this entry maps.
92 Addr vaddr;
93 // The size of the page this entry represents.
94 Addr size;
95
96 // Read permission is always available, assuming it isn't blocked by
97 // other mechanisms.
98 bool writable;
99 // Whether this page is accesible without being in supervisor mode.
100 bool user;
101 // Whether to use write through or write back. M5 ignores this and
102 // lets the caches handle the writeback policy.
103 //bool pwt;
104 // Whether the page is cacheable or not.
105 bool uncacheable;
106 // Whether or not to kick this page out on a write to CR3.
107 bool global;
108 // A bit used to form an index into the PAT table.
109 bool patBit;
110 // Whether or not memory on this page can be executed.
111 bool noExec;
112
113 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
114 TlbEntry() {}
115
116 void
117 updateVaddr(Addr new_vaddr)
118 {
119 vaddr = new_vaddr;
120 }
121
122 Addr pageStart()
123 {
124 return paddr;
125 }
126
127 void serialize(std::ostream &os);
128 void unserialize(Checkpoint *cp, const std::string &section);
129 };
130 }
131
132 #endif