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40 #ifndef __ARCH_X86_PAGETABLE_HH__
41 #define __ARCH_X86_PAGETABLE_HH__
46 #include "base/bitunion.hh"
47 #include "base/misc.hh"
48 #include "base/types.hh"
49 #include "base/trie.hh"
58 typedef Trie<Addr, X86ISA::TlbEntry> TlbEntryTrie;
63 Bitfield<20, 12> longl1;
64 Bitfield<29, 21> longl2;
65 Bitfield<38, 30> longl3;
66 Bitfield<47, 39> longl4;
68 Bitfield<20, 12> pael1;
69 Bitfield<29, 21> pael2;
70 Bitfield<31, 30> pael3;
72 Bitfield<21, 12> norml1;
73 Bitfield<31, 22> norml2;
78 // The base of the physical page.
81 // The beginning of the virtual page this entry maps.
83 // The size of the page this represents, in address bits.
86 // Read permission is always available, assuming it isn't blocked by
89 // Whether this page is accesible without being in supervisor mode.
91 // Whether to use write through or write back. M5 ignores this and
92 // lets the caches handle the writeback policy.
94 // Whether the page is cacheable or not.
96 // Whether or not to kick this page out on a write to CR3.
98 // A bit used to form an index into the PAT table.
100 // Whether or not memory on this page can be executed.
102 // A sequence number to keep track of LRU.
105 TlbEntryTrie::Handle trieHandle;
107 TlbEntry(Addr asn, Addr _vaddr, Addr _paddr);
111 updateVaddr(Addr new_vaddr)
121 void serialize(std::ostream &os);
122 void unserialize(Checkpoint *cp, const std::string §ion);