2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 #include "arch/x86/pagetable.hh"
53 #include "arch/x86/pagetable_walker.hh"
54 #include "arch/x86/tlb.hh"
55 #include "arch/x86/vtophys.hh"
56 #include "base/bitfield.hh"
57 #include "cpu/base.hh"
58 #include "cpu/thread_context.hh"
59 #include "debug/PageTableWalker.hh"
60 #include "mem/packet_access.hh"
61 #include "mem/request.hh"
62 #include "sim/system.hh"
66 // Unfortunately, the placement of the base field in a page table entry is
67 // very erratic and would make a mess here. It might be moved here at some
68 // point in the future.
69 BitUnion64(PageTableEntry
)
81 EndBitUnion(PageTableEntry
)
84 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
85 RequestPtr _req
, BaseTLB::Mode _mode
)
87 // TODO: in timing mode, instead of blocking when there are other
88 // outstanding requests, see if this request can be coalesced with
89 // another one (i.e. either coalesce or start walk)
90 WalkerState
* newState
= new WalkerState(this, _translation
, _req
);
91 newState
->initState(_tc
, _mode
, sys
->getMemoryMode() == Enums::timing
);
92 if (currStates
.size()) {
93 assert(newState
->isTiming());
94 DPRINTF(PageTableWalker
, "Walks in progress: %d\n", currStates
.size());
95 currStates
.push_back(newState
);
98 currStates
.push_back(newState
);
99 Fault fault
= newState
->startWalk();
100 if (!newState
->isTiming()) {
101 currStates
.pop_front();
109 Walker::startFunctional(ThreadContext
* _tc
, Addr
&addr
, Addr
&pageSize
,
112 funcState
.initState(_tc
, _mode
);
113 return funcState
.startFunctional(addr
, pageSize
);
117 Walker::WalkerPort::recvTiming(PacketPtr pkt
)
119 return walker
->recvTiming(pkt
);
123 Walker::recvTiming(PacketPtr pkt
)
125 assert(pkt
->isResponse());
126 WalkerSenderState
* senderState
=
127 dynamic_cast<WalkerSenderState
*>(pkt
->senderState
);
128 pkt
->senderState
= senderState
->saved
;
129 WalkerState
* senderWalk
= senderState
->senderWalk
;
130 bool walkComplete
= senderWalk
->recvPacket(pkt
);
133 std::list
<WalkerState
*>::iterator iter
;
134 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
135 WalkerState
* walkerState
= *(iter
);
136 if (walkerState
== senderWalk
) {
137 iter
= currStates
.erase(iter
);
142 // Since we block requests when another is outstanding, we
143 // need to check if there is a waiting request to be serviced
144 if (currStates
.size()) {
145 WalkerState
* newState
= currStates
.front();
146 if (!newState
->wasStarted())
147 newState
->startWalk();
154 Walker::WalkerPort::recvRetry()
162 std::list
<WalkerState
*>::iterator iter
;
163 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
164 WalkerState
* walkerState
= *(iter
);
165 if (walkerState
->isRetrying()) {
166 walkerState
->retry();
171 bool Walker::sendTiming(WalkerState
* sendingState
, PacketPtr pkt
)
173 pkt
->senderState
= new WalkerSenderState(sendingState
, pkt
->senderState
);
174 return port
.sendTiming(pkt
);
178 Walker::getMasterPort(const std::string
&if_name
, int idx
)
180 if (if_name
== "port")
183 return MemObject::getMasterPort(if_name
, idx
);
187 Walker::WalkerState::initState(ThreadContext
* _tc
,
188 BaseTLB::Mode _mode
, bool _isTiming
)
190 assert(state
== Ready
);
198 Walker::WalkerState::startWalk()
200 Fault fault
= NoFault
;
201 assert(started
== false);
203 setupWalk(req
->getVaddr());
207 timingFault
= NoFault
;
211 walker
->port
.sendAtomic(read
);
212 PacketPtr write
= NULL
;
213 fault
= stepWalk(write
);
214 assert(fault
== NoFault
|| read
== NULL
);
218 walker
->port
.sendAtomic(write
);
227 Walker::WalkerState::startFunctional(Addr
&addr
, Addr
&pageSize
)
229 Fault fault
= NoFault
;
230 assert(started
== false);
235 walker
->port
.sendFunctional(read
);
236 // On a functional access (page table lookup), writes should
237 // not happen so this pointer is ignored after stepWalk
238 PacketPtr write
= NULL
;
239 fault
= stepWalk(write
);
240 assert(fault
== NoFault
|| read
== NULL
);
244 pageSize
= entry
.size
;
251 Walker::WalkerState::stepWalk(PacketPtr
&write
)
253 assert(state
!= Ready
&& state
!= Waiting
);
254 Fault fault
= NoFault
;
258 pte
= read
->get
<uint64_t>();
260 pte
= read
->get
<uint32_t>();
261 VAddr vaddr
= entry
.vaddr
;
262 bool uncacheable
= pte
.pcd
;
264 bool doWrite
= false;
265 bool doTLBInsert
= false;
266 bool doEndWalk
= false;
267 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
270 DPRINTF(PageTableWalker
,
271 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
272 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* dataSize
;
275 entry
.writable
= pte
.w
;
277 if (badNX
|| !pte
.p
) {
279 fault
= pageFault(pte
.p
);
282 entry
.noExec
= pte
.nx
;
286 DPRINTF(PageTableWalker
,
287 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
288 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* dataSize
;
291 entry
.writable
= entry
.writable
&& pte
.w
;
292 entry
.user
= entry
.user
&& pte
.u
;
293 if (badNX
|| !pte
.p
) {
295 fault
= pageFault(pte
.p
);
301 DPRINTF(PageTableWalker
,
302 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
305 entry
.writable
= entry
.writable
&& pte
.w
;
306 entry
.user
= entry
.user
&& pte
.u
;
307 if (badNX
|| !pte
.p
) {
309 fault
= pageFault(pte
.p
);
314 entry
.size
= 4 * (1 << 10);
316 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* dataSize
;
321 entry
.size
= 2 * (1 << 20);
322 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
323 entry
.uncacheable
= uncacheable
;
324 entry
.global
= pte
.g
;
325 entry
.patBit
= bits(pte
, 12);
326 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
332 DPRINTF(PageTableWalker
,
333 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
336 entry
.writable
= entry
.writable
&& pte
.w
;
337 entry
.user
= entry
.user
&& pte
.u
;
338 if (badNX
|| !pte
.p
) {
340 fault
= pageFault(pte
.p
);
343 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
344 entry
.uncacheable
= uncacheable
;
345 entry
.global
= pte
.g
;
346 entry
.patBit
= bits(pte
, 12);
347 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
352 DPRINTF(PageTableWalker
,
353 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
354 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* dataSize
;
357 fault
= pageFault(pte
.p
);
363 DPRINTF(PageTableWalker
,
364 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
367 entry
.writable
= pte
.w
;
369 if (badNX
|| !pte
.p
) {
371 fault
= pageFault(pte
.p
);
376 entry
.size
= 4 * (1 << 10);
377 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* dataSize
;
382 entry
.size
= 2 * (1 << 20);
383 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
384 entry
.uncacheable
= uncacheable
;
385 entry
.global
= pte
.g
;
386 entry
.patBit
= bits(pte
, 12);
387 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
393 DPRINTF(PageTableWalker
,
394 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
397 entry
.writable
= entry
.writable
&& pte
.w
;
398 entry
.user
= entry
.user
&& pte
.u
;
399 if (badNX
|| !pte
.p
) {
401 fault
= pageFault(pte
.p
);
404 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
405 entry
.uncacheable
= uncacheable
;
406 entry
.global
= pte
.g
;
407 entry
.patBit
= bits(pte
, 7);
408 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
413 DPRINTF(PageTableWalker
,
414 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
417 entry
.writable
= pte
.w
;
421 fault
= pageFault(pte
.p
);
426 entry
.size
= 4 * (1 << 10);
428 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
433 entry
.size
= 4 * (1 << 20);
434 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
435 entry
.uncacheable
= uncacheable
;
436 entry
.global
= pte
.g
;
437 entry
.patBit
= bits(pte
, 12);
438 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
444 DPRINTF(PageTableWalker
,
445 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
448 entry
.writable
= pte
.w
;
452 fault
= pageFault(pte
.p
);
456 entry
.size
= 4 * (1 << 10);
457 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
461 DPRINTF(PageTableWalker
,
462 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
465 entry
.writable
= pte
.w
;
469 fault
= pageFault(pte
.p
);
472 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
473 entry
.uncacheable
= uncacheable
;
474 entry
.global
= pte
.g
;
475 entry
.patBit
= bits(pte
, 7);
476 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
481 panic("Unknown page table walker state %d!\n");
486 walker
->tlb
->insert(entry
.vaddr
, entry
);
489 PacketPtr oldRead
= read
;
490 //If we didn't return, we're setting up another read.
491 Request::Flags flags
= oldRead
->req
->getFlags();
492 flags
.set(Request::UNCACHEABLE
, uncacheable
);
494 new Request(nextRead
, oldRead
->getSize(), flags
, walker
->masterId
);
495 read
= new Packet(request
, MemCmd::ReadReq
);
497 // If we need to write, adjust the read packet to write the modified
498 // value back to memory.
501 write
->set
<uint64_t>(pte
);
502 write
->cmd
= MemCmd::WriteReq
;
514 Walker::WalkerState::endWalk()
523 Walker::WalkerState::setupWalk(Addr vaddr
)
526 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
527 // Check if we're in long mode or not
528 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
534 topAddr
= (cr3
.longPdtb
<< 12) + addr
.longl4
* dataSize
;
537 // We're in some flavor of legacy mode.
538 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
542 topAddr
= (cr3
.paePdtb
<< 5) + addr
.pael3
* dataSize
;
546 topAddr
= (cr3
.pdtb
<< 12) + addr
.norml2
* dataSize
;
551 // Do legacy non PSE.
561 Request::Flags flags
= Request::PHYSICAL
;
563 flags
.set(Request::UNCACHEABLE
);
564 RequestPtr request
= new Request(topAddr
, dataSize
, flags
,
566 read
= new Packet(request
, MemCmd::ReadReq
);
571 Walker::WalkerState::recvPacket(PacketPtr pkt
)
573 assert(pkt
->isResponse());
574 if (!pkt
->wasNacked()) {
576 assert(state
== Waiting
);
582 PacketPtr write
= NULL
;
584 timingFault
= stepWalk(write
);
586 assert(timingFault
== NoFault
|| read
== NULL
);
588 writes
.push_back(write
);
594 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
597 if (timingFault
== NoFault
) {
599 * Finish the translation. Now that we now the right entry is
600 * in the TLB, this should work with no memory accesses.
601 * There could be new faults unrelated to the table walk like
602 * permissions violations, so we'll need the return value as
605 bool delayedResponse
;
606 Fault fault
= walker
->tlb
->translate(req
, tc
, NULL
, mode
,
607 delayedResponse
, true);
608 assert(!delayedResponse
);
609 // Let the CPU continue.
610 translation
->finish(fault
, req
, tc
, mode
);
612 // There was a fault during the walk. Let the CPU know.
613 translation
->finish(timingFault
, req
, tc
, mode
);
618 DPRINTF(PageTableWalker
, "Request was nacked. Entering retry state\n");
620 if (!walker
->sendTiming(this, pkt
)) {
623 if (pkt
->isWrite()) {
624 writes
.push_back(pkt
);
635 Walker::WalkerState::sendPackets()
637 //If we're already waiting for the port to become available, just return.
641 //Reads always have priority
643 PacketPtr pkt
= read
;
646 if (!walker
->sendTiming(this, pkt
)) {
653 //Send off as many of the writes as we can.
654 while (writes
.size()) {
655 PacketPtr write
= writes
.back();
658 if (!walker
->sendTiming(this, write
)) {
660 writes
.push_back(write
);
668 Walker::WalkerState::isRetrying()
674 Walker::WalkerState::isTiming()
680 Walker::WalkerState::wasStarted()
686 Walker::WalkerState::retry()
693 Walker::WalkerState::pageFault(bool present
)
695 DPRINTF(PageTableWalker
, "Raising page fault.\n");
696 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
697 if (mode
== BaseTLB::Execute
&& !enableNX
)
698 mode
= BaseTLB::Read
;
699 return new PageFault(entry
.vaddr
, present
, mode
, m5reg
.cpl
== 3, false);
702 /* end namespace X86ISA */ }
705 X86PagetableWalkerParams::create()
707 return new X86ISA::Walker(this);