src/arch/x86/pagetable_walker.cc

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 The Hewlett-Packard Development Company
  15  * All rights reserved.
  16  *
  17  * The license below extends only to copyright in the software and shall
  18  * not be construed as granting a license to any other intellectual
  19  * property including but not limited to intellectual property relating
  20  * to a hardware implementation of the functionality of the software
  21  * licensed hereunder.  You may use the software subject to the license
  22  * terms below provided that you ensure that this notice is replicated
  23  * unmodified and in its entirety in all distributions of the software,
  24  * modified or unmodified, in source code or in binary form.
  25  *
  26  * Redistribution and use in source and binary forms, with or without
  27  * modification, are permitted provided that the following conditions are
  28  * met: redistributions of source code must retain the above copyright
  29  * notice, this list of conditions and the following disclaimer;
  30  * redistributions in binary form must reproduce the above copyright
  31  * notice, this list of conditions and the following disclaimer in the
  32  * documentation and/or other materials provided with the distribution;
  33  * neither the name of the copyright holders nor the names of its
  34  * contributors may be used to endorse or promote products derived from
  35  * this software without specific prior written permission.
  36  *
  37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48  *
  49  * Authors: Gabe Black
  50  */
  51
  52 #include "arch/x86/pagetable_walker.hh"
  53
  54 #include <memory>
  55
  56 #include "arch/x86/faults.hh"
  57 #include "arch/x86/pagetable.hh"
  58 #include "arch/x86/tlb.hh"
  59 #include "arch/x86/vtophys.hh"
  60 #include "base/bitfield.hh"
  61 #include "base/trie.hh"
  62 #include "cpu/base.hh"
  63 #include "cpu/thread_context.hh"
  64 #include "debug/PageTableWalker.hh"
  65 #include "mem/packet_access.hh"
  66 #include "mem/request.hh"
  67
  68 namespace X86ISA {
  69
  70 Fault
  71 Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation,
  72               const RequestPtr &_req, BaseTLB::Mode _mode)
  73 {
  74     // TODO: in timing mode, instead of blocking when there are other
  75     // outstanding requests, see if this request can be coalesced with
  76     // another one (i.e. either coalesce or start walk)
  77     WalkerState * newState = new WalkerState(this, _translation, _req);
  78     newState->initState(_tc, _mode, sys->isTimingMode());
  79     if (currStates.size()) {
  80         assert(newState->isTiming());
  81         DPRINTF(PageTableWalker, "Walks in progress: %d\n", currStates.size());
  82         currStates.push_back(newState);
  83         return NoFault;
  84     } else {
  85         currStates.push_back(newState);
  86         Fault fault = newState->startWalk();
  87         if (!newState->isTiming()) {
  88             currStates.pop_front();
  89             delete newState;
  90         }
  91         return fault;
  92     }
  93 }
  94
  95 Fault
  96 Walker::startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes,
  97               BaseTLB::Mode _mode)
  98 {
  99     funcState.initState(_tc, _mode);
 100     return funcState.startFunctional(addr, logBytes);
 101 }
 102
 103 bool
 104 Walker::WalkerPort::recvTimingResp(PacketPtr pkt)
 105 {
 106     return walker->recvTimingResp(pkt);
 107 }
 108
 109 bool
 110 Walker::recvTimingResp(PacketPtr pkt)
 111 {
 112     WalkerSenderState * senderState =
 113         dynamic_cast<WalkerSenderState *>(pkt->popSenderState());
 114     WalkerState * senderWalk = senderState->senderWalk;
 115     bool walkComplete = senderWalk->recvPacket(pkt);
 116     delete senderState;
 117     if (walkComplete) {
 118         std::list<WalkerState *>::iterator iter;
 119         for (iter = currStates.begin(); iter != currStates.end(); iter++) {
 120             WalkerState * walkerState = *(iter);
 121             if (walkerState == senderWalk) {
 122                 iter = currStates.erase(iter);
 123                 break;
 124             }
 125         }
 126         delete senderWalk;
 127         // Since we block requests when another is outstanding, we
 128         // need to check if there is a waiting request to be serviced
 129         if (currStates.size() && !startWalkWrapperEvent.scheduled())
 130             // delay sending any new requests until we are finished
 131             // with the responses
 132             schedule(startWalkWrapperEvent, clockEdge());
 133     }
 134     return true;
 135 }
 136
 137 void
 138 Walker::WalkerPort::recvReqRetry()
 139 {
 140     walker->recvReqRetry();
 141 }
 142
 143 void
 144 Walker::recvReqRetry()
 145 {
 146     std::list<WalkerState *>::iterator iter;
 147     for (iter = currStates.begin(); iter != currStates.end(); iter++) {
 148         WalkerState * walkerState = *(iter);
 149         if (walkerState->isRetrying()) {
 150             walkerState->retry();
 151         }
 152     }
 153 }
 154
 155 bool Walker::sendTiming(WalkerState* sendingState, PacketPtr pkt)
 156 {
 157     WalkerSenderState* walker_state = new WalkerSenderState(sendingState);
 158     pkt->pushSenderState(walker_state);
 159     if (port.sendTimingReq(pkt)) {
 160         return true;
 161     } else {
 162         // undo the adding of the sender state and delete it, as we
 163         // will do it again the next time we attempt to send it
 164         pkt->popSenderState();
 165         delete walker_state;
 166         return false;
 167     }
 168
 169 }
 170
 171 Port &
 172 Walker::getPort(const std::string &if_name, PortID idx)
 173 {
 174     if (if_name == "port")
 175         return port;
 176     else
 177         return ClockedObject::getPort(if_name, idx);
 178 }
 179
 180 void
 181 Walker::WalkerState::initState(ThreadContext * _tc,
 182         BaseTLB::Mode _mode, bool _isTiming)
 183 {
 184     assert(state == Ready);
 185     started = false;
 186     tc = _tc;
 187     mode = _mode;
 188     timing = _isTiming;
 189 }
 190
 191 void
 192 Walker::startWalkWrapper()
 193 {
 194     unsigned num_squashed = 0;
 195     WalkerState *currState = currStates.front();
 196     while ((num_squashed < numSquashable) && currState &&
 197         currState->translation->squashed()) {
 198         currStates.pop_front();
 199         num_squashed++;
 200
 201         DPRINTF(PageTableWalker, "Squashing table walk for address %#x\n",
 202             currState->req->getVaddr());
 203
 204         // finish the translation which will delete the translation object
 205         currState->translation->finish(
 206             std::make_shared<UnimpFault>("Squashed Inst"),
 207             currState->req, currState->tc, currState->mode);
 208
 209         // delete the current request if there are no inflight packets.
 210         // if there is something in flight, delete when the packets are
 211         // received and inflight is zero.
 212         if (currState->numInflight() == 0) {
 213             delete currState;
 214         } else {
 215             currState->squash();
 216         }
 217
 218         // check the next translation request, if it exists
 219         if (currStates.size())
 220             currState = currStates.front();
 221         else
 222             currState = NULL;
 223     }
 224     if (currState && !currState->wasStarted())
 225         currState->startWalk();
 226 }
 227
 228 Fault
 229 Walker::WalkerState::startWalk()
 230 {
 231     Fault fault = NoFault;
 232     assert(!started);
 233     started = true;
 234     setupWalk(req->getVaddr());
 235     if (timing) {
 236         nextState = state;
 237         state = Waiting;
 238         timingFault = NoFault;
 239         sendPackets();
 240     } else {
 241         do {
 242             walker->port.sendAtomic(read);
 243             PacketPtr write = NULL;
 244             fault = stepWalk(write);
 245             assert(fault == NoFault || read == NULL);
 246             state = nextState;
 247             nextState = Ready;
 248             if (write)
 249                 walker->port.sendAtomic(write);
 250         } while (read);
 251         state = Ready;
 252         nextState = Waiting;
 253     }
 254     return fault;
 255 }
 256
 257 Fault
 258 Walker::WalkerState::startFunctional(Addr &addr, unsigned &logBytes)
 259 {
 260     Fault fault = NoFault;
 261     assert(!started);
 262     started = true;
 263     setupWalk(addr);
 264
 265     do {
 266         walker->port.sendFunctional(read);
 267         // On a functional access (page table lookup), writes should
 268         // not happen so this pointer is ignored after stepWalk
 269         PacketPtr write = NULL;
 270         fault = stepWalk(write);
 271         assert(fault == NoFault || read == NULL);
 272         state = nextState;
 273         nextState = Ready;
 274     } while (read);
 275     logBytes = entry.logBytes;
 276     addr = entry.paddr;
 277
 278     return fault;
 279 }
 280
 281 Fault
 282 Walker::WalkerState::stepWalk(PacketPtr &write)
 283 {
 284     assert(state != Ready && state != Waiting);
 285     Fault fault = NoFault;
 286     write = NULL;
 287     PageTableEntry pte;
 288     if (dataSize == 8)
 289         pte = read->getLE<uint64_t>();
 290     else
 291         pte = read->getLE<uint32_t>();
 292     VAddr vaddr = entry.vaddr;
 293     bool uncacheable = pte.pcd;
 294     Addr nextRead = 0;
 295     bool doWrite = false;
 296     bool doTLBInsert = false;
 297     bool doEndWalk = false;
 298     bool badNX = pte.nx && mode == BaseTLB::Execute && enableNX;
 299     switch(state) {
 300       case LongPML4:
 301         DPRINTF(PageTableWalker,
 302                 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte);
 303         nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 * dataSize;
 304         doWrite = !pte.a;
 305         pte.a = 1;
 306         entry.writable = pte.w;
 307         entry.user = pte.u;
 308         if (badNX || !pte.p) {
 309             doEndWalk = true;
 310             fault = pageFault(pte.p);
 311             break;
 312         }
 313         entry.noExec = pte.nx;
 314         nextState = LongPDP;
 315         break;
 316       case LongPDP:
 317         DPRINTF(PageTableWalker,
 318                 "Got long mode PDP entry %#016x.\n", (uint64_t)pte);
 319         nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 * dataSize;
 320         doWrite = !pte.a;
 321         pte.a = 1;
 322         entry.writable = entry.writable && pte.w;
 323         entry.user = entry.user && pte.u;
 324         if (badNX || !pte.p) {
 325             doEndWalk = true;
 326             fault = pageFault(pte.p);
 327             break;
 328         }
 329         nextState = LongPD;
 330         break;
 331       case LongPD:
 332         DPRINTF(PageTableWalker,
 333                 "Got long mode PD entry %#016x.\n", (uint64_t)pte);
 334         doWrite = !pte.a;
 335         pte.a = 1;
 336         entry.writable = entry.writable && pte.w;
 337         entry.user = entry.user && pte.u;
 338         if (badNX || !pte.p) {
 339             doEndWalk = true;
 340             fault = pageFault(pte.p);
 341             break;
 342         }
 343         if (!pte.ps) {
 344             // 4 KB page
 345             entry.logBytes = 12;
 346             nextRead =
 347                 ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 * dataSize;
 348             nextState = LongPTE;
 349             break;
 350         } else {
 351             // 2 MB page
 352             entry.logBytes = 21;
 353             entry.paddr = (uint64_t)pte & (mask(31) << 21);
 354             entry.uncacheable = uncacheable;
 355             entry.global = pte.g;
 356             entry.patBit = bits(pte, 12);
 357             entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
 358             doTLBInsert = true;
 359             doEndWalk = true;
 360             break;
 361         }
 362       case LongPTE:
 363         DPRINTF(PageTableWalker,
 364                 "Got long mode PTE entry %#016x.\n", (uint64_t)pte);
 365         doWrite = !pte.a;
 366         pte.a = 1;
 367         entry.writable = entry.writable && pte.w;
 368         entry.user = entry.user && pte.u;
 369         if (badNX || !pte.p) {
 370             doEndWalk = true;
 371             fault = pageFault(pte.p);
 372             break;
 373         }
 374         entry.paddr = (uint64_t)pte & (mask(40) << 12);
 375         entry.uncacheable = uncacheable;
 376         entry.global = pte.g;
 377         entry.patBit = bits(pte, 12);
 378         entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
 379         doTLBInsert = true;
 380         doEndWalk = true;
 381         break;
 382       case PAEPDP:
 383         DPRINTF(PageTableWalker,
 384                 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte);
 385         nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael2 * dataSize;
 386         if (!pte.p) {
 387             doEndWalk = true;
 388             fault = pageFault(pte.p);
 389             break;
 390         }
 391         nextState = PAEPD;
 392         break;
 393       case PAEPD:
 394         DPRINTF(PageTableWalker,
 395                 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte);
 396         doWrite = !pte.a;
 397         pte.a = 1;
 398         entry.writable = pte.w;
 399         entry.user = pte.u;
 400         if (badNX || !pte.p) {
 401             doEndWalk = true;
 402             fault = pageFault(pte.p);
 403             break;
 404         }
 405         if (!pte.ps) {
 406             // 4 KB page
 407             entry.logBytes = 12;
 408             nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael1 * dataSize;
 409             nextState = PAEPTE;
 410             break;
 411         } else {
 412             // 2 MB page
 413             entry.logBytes = 21;
 414             entry.paddr = (uint64_t)pte & (mask(31) << 21);
 415             entry.uncacheable = uncacheable;
 416             entry.global = pte.g;
 417             entry.patBit = bits(pte, 12);
 418             entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
 419             doTLBInsert = true;
 420             doEndWalk = true;
 421             break;
 422         }
 423       case PAEPTE:
 424         DPRINTF(PageTableWalker,
 425                 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte);
 426         doWrite = !pte.a;
 427         pte.a = 1;
 428         entry.writable = entry.writable && pte.w;
 429         entry.user = entry.user && pte.u;
 430         if (badNX || !pte.p) {
 431             doEndWalk = true;
 432             fault = pageFault(pte.p);
 433             break;
 434         }
 435         entry.paddr = (uint64_t)pte & (mask(40) << 12);
 436         entry.uncacheable = uncacheable;
 437         entry.global = pte.g;
 438         entry.patBit = bits(pte, 7);
 439         entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
 440         doTLBInsert = true;
 441         doEndWalk = true;
 442         break;
 443       case PSEPD:
 444         DPRINTF(PageTableWalker,
 445                 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte);
 446         doWrite = !pte.a;
 447         pte.a = 1;
 448         entry.writable = pte.w;
 449         entry.user = pte.u;
 450         if (!pte.p) {
 451             doEndWalk = true;
 452             fault = pageFault(pte.p);
 453             break;
 454         }
 455         if (!pte.ps) {
 456             // 4 KB page
 457             entry.logBytes = 12;
 458             nextRead =
 459                 ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
 460             nextState = PTE;
 461             break;
 462         } else {
 463             // 4 MB page
 464             entry.logBytes = 21;
 465             entry.paddr = bits(pte, 20, 13) << 32 | bits(pte, 31, 22) << 22;
 466             entry.uncacheable = uncacheable;
 467             entry.global = pte.g;
 468             entry.patBit = bits(pte, 12);
 469             entry.vaddr = entry.vaddr & ~((4 * (1 << 20)) - 1);
 470             doTLBInsert = true;
 471             doEndWalk = true;
 472             break;
 473         }
 474       case PD:
 475         DPRINTF(PageTableWalker,
 476                 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte);
 477         doWrite = !pte.a;
 478         pte.a = 1;
 479         entry.writable = pte.w;
 480         entry.user = pte.u;
 481         if (!pte.p) {
 482             doEndWalk = true;
 483             fault = pageFault(pte.p);
 484             break;
 485         }
 486         // 4 KB page
 487         entry.logBytes = 12;
 488         nextRead = ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * dataSize;
 489         nextState = PTE;
 490         break;
 491       case PTE:
 492         DPRINTF(PageTableWalker,
 493                 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte);
 494         doWrite = !pte.a;
 495         pte.a = 1;
 496         entry.writable = pte.w;
 497         entry.user = pte.u;
 498         if (!pte.p) {
 499             doEndWalk = true;
 500             fault = pageFault(pte.p);
 501             break;
 502         }
 503         entry.paddr = (uint64_t)pte & (mask(20) << 12);
 504         entry.uncacheable = uncacheable;
 505         entry.global = pte.g;
 506         entry.patBit = bits(pte, 7);
 507         entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
 508         doTLBInsert = true;
 509         doEndWalk = true;
 510         break;
 511       default:
 512         panic("Unknown page table walker state %d!\n");
 513     }
 514     if (doEndWalk) {
 515         if (doTLBInsert)
 516             if (!functional)
 517                 walker->tlb->insert(entry.vaddr, entry);
 518         endWalk();
 519     } else {
 520         PacketPtr oldRead = read;
 521         //If we didn't return, we're setting up another read.
 522         Request::Flags flags = oldRead->req->getFlags();
 523         flags.set(Request::UNCACHEABLE, uncacheable);
 524         RequestPtr request = std::make_shared<Request>(
 525             nextRead, oldRead->getSize(), flags, walker->masterId);
 526         read = new Packet(request, MemCmd::ReadReq);
 527         read->allocate();
 528         // If we need to write, adjust the read packet to write the modified
 529         // value back to memory.
 530         if (doWrite) {
 531             write = oldRead;
 532             write->setLE<uint64_t>(pte);
 533             write->cmd = MemCmd::WriteReq;
 534         } else {
 535             write = NULL;
 536             delete oldRead;
 537         }
 538     }
 539     return fault;
 540 }
 541
 542 void
 543 Walker::WalkerState::endWalk()
 544 {
 545     nextState = Ready;
 546     delete read;
 547     read = NULL;
 548 }
 549
 550 void
 551 Walker::WalkerState::setupWalk(Addr vaddr)
 552 {
 553     VAddr addr = vaddr;
 554     CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
 555     // Check if we're in long mode or not
 556     Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
 557     dataSize = 8;
 558     Addr topAddr;
 559     if (efer.lma) {
 560         // Do long mode.
 561         state = LongPML4;
 562         topAddr = (cr3.longPdtb << 12) + addr.longl4 * dataSize;
 563         enableNX = efer.nxe;
 564     } else {
 565         // We're in some flavor of legacy mode.
 566         CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
 567         if (cr4.pae) {
 568             // Do legacy PAE.
 569             state = PAEPDP;
 570             topAddr = (cr3.paePdtb << 5) + addr.pael3 * dataSize;
 571             enableNX = efer.nxe;
 572         } else {
 573             dataSize = 4;
 574             topAddr = (cr3.pdtb << 12) + addr.norml2 * dataSize;
 575             if (cr4.pse) {
 576                 // Do legacy PSE.
 577                 state = PSEPD;
 578             } else {
 579                 // Do legacy non PSE.
 580                 state = PD;
 581             }
 582             enableNX = false;
 583         }
 584     }
 585
 586     nextState = Ready;
 587     entry.vaddr = vaddr;
 588
 589     Request::Flags flags = Request::PHYSICAL;
 590     if (cr3.pcd)
 591         flags.set(Request::UNCACHEABLE);
 592
 593     RequestPtr request = std::make_shared<Request>(
 594         topAddr, dataSize, flags, walker->masterId);
 595
 596     read = new Packet(request, MemCmd::ReadReq);
 597     read->allocate();
 598 }
 599
 600 bool
 601 Walker::WalkerState::recvPacket(PacketPtr pkt)
 602 {
 603     assert(pkt->isResponse());
 604     assert(inflight);
 605     assert(state == Waiting);
 606     inflight--;
 607     if (squashed) {
 608         // if were were squashed, return true once inflight is zero and
 609         // this WalkerState will be freed there.
 610         return (inflight == 0);
 611     }
 612     if (pkt->isRead()) {
 613         // should not have a pending read it we also had one outstanding
 614         assert(!read);
 615
 616         // @todo someone should pay for this
 617         pkt->headerDelay = pkt->payloadDelay = 0;
 618
 619         state = nextState;
 620         nextState = Ready;
 621         PacketPtr write = NULL;
 622         read = pkt;
 623         timingFault = stepWalk(write);
 624         state = Waiting;
 625         assert(timingFault == NoFault || read == NULL);
 626         if (write) {
 627             writes.push_back(write);
 628         }
 629         sendPackets();
 630     } else {
 631         sendPackets();
 632     }
 633     if (inflight == 0 && read == NULL && writes.size() == 0) {
 634         state = Ready;
 635         nextState = Waiting;
 636         if (timingFault == NoFault) {
 637             /*
 638              * Finish the translation. Now that we know the right entry is
 639              * in the TLB, this should work with no memory accesses.
 640              * There could be new faults unrelated to the table walk like
 641              * permissions violations, so we'll need the return value as
 642              * well.
 643              */
 644             bool delayedResponse;
 645             Fault fault = walker->tlb->translate(req, tc, NULL, mode,
 646                                                  delayedResponse, true);
 647             assert(!delayedResponse);
 648             // Let the CPU continue.
 649             translation->finish(fault, req, tc, mode);
 650         } else {
 651             // There was a fault during the walk. Let the CPU know.
 652             translation->finish(timingFault, req, tc, mode);
 653         }
 654         return true;
 655     }
 656
 657     return false;
 658 }
 659
 660 void
 661 Walker::WalkerState::sendPackets()
 662 {
 663     //If we're already waiting for the port to become available, just return.
 664     if (retrying)
 665         return;
 666
 667     //Reads always have priority
 668     if (read) {
 669         PacketPtr pkt = read;
 670         read = NULL;
 671         inflight++;
 672         if (!walker->sendTiming(this, pkt)) {
 673             retrying = true;
 674             read = pkt;
 675             inflight--;
 676             return;
 677         }
 678     }
 679     //Send off as many of the writes as we can.
 680     while (writes.size()) {
 681         PacketPtr write = writes.back();
 682         writes.pop_back();
 683         inflight++;
 684         if (!walker->sendTiming(this, write)) {
 685             retrying = true;
 686             writes.push_back(write);
 687             inflight--;
 688             return;
 689         }
 690     }
 691 }
 692
 693 unsigned
 694 Walker::WalkerState::numInflight() const
 695 {
 696     return inflight;
 697 }
 698
 699 bool
 700 Walker::WalkerState::isRetrying()
 701 {
 702     return retrying;
 703 }
 704
 705 bool
 706 Walker::WalkerState::isTiming()
 707 {
 708     return timing;
 709 }
 710
 711 bool
 712 Walker::WalkerState::wasStarted()
 713 {
 714     return started;
 715 }
 716
 717 void
 718 Walker::WalkerState::squash()
 719 {
 720     squashed = true;
 721 }
 722
 723 void
 724 Walker::WalkerState::retry()
 725 {
 726     retrying = false;
 727     sendPackets();
 728 }
 729
 730 Fault
 731 Walker::WalkerState::pageFault(bool present)
 732 {
 733     DPRINTF(PageTableWalker, "Raising page fault.\n");
 734     HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
 735     if (mode == BaseTLB::Execute && !enableNX)
 736         mode = BaseTLB::Read;
 737     return std::make_shared<PageFault>(entry.vaddr, present, mode,
 738                                        m5reg.cpl == 3, false);
 739 }
 740
 741 /* end namespace X86ISA */ }
 742
 743 X86ISA::Walker *
 744 X86PagetableWalkerParams::create()
 745 {
 746     return new X86ISA::Walker(this);
 747 }