cf82727a974f5e5d8e4f8b182d3e6fd0c25b6e8a
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
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15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
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18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
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21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/x86/pagetable.hh"
41 #include "arch/x86/pagetable_walker.hh"
42 #include "arch/x86/tlb.hh"
43 #include "base/bitfield.hh"
44 #include "cpu/thread_context.hh"
45 #include "cpu/base.hh"
46 #include "mem/packet_access.hh"
47 #include "mem/request.hh"
48 #include "sim/system.hh"
52 // Unfortunately, the placement of the base field in a page table entry is
53 // very erratic and would make a mess here. It might be moved here at some
54 // point in the future.
55 BitUnion64(PageTableEntry
)
67 EndBitUnion(PageTableEntry
)
70 Walker::doNext(PacketPtr
&write
)
72 assert(state
!= Ready
&& state
!= Waiting
);
76 pte
= read
->get
<uint64_t>();
78 pte
= read
->get
<uint32_t>();
79 VAddr vaddr
= entry
.vaddr
;
80 bool uncacheable
= pte
.pcd
;
83 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
86 DPRINTF(PageTableWalker
,
87 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
88 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* size
;
91 entry
.writable
= pte
.w
;
93 if (badNX
|| !pte
.p
) {
95 return pageFault(pte
.p
);
97 entry
.noExec
= pte
.nx
;
101 DPRINTF(PageTableWalker
,
102 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
103 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* size
;
106 entry
.writable
= entry
.writable
&& pte
.w
;
107 entry
.user
= entry
.user
&& pte
.u
;
108 if (badNX
|| !pte
.p
) {
110 return pageFault(pte
.p
);
115 DPRINTF(PageTableWalker
,
116 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
119 entry
.writable
= entry
.writable
&& pte
.w
;
120 entry
.user
= entry
.user
&& pte
.u
;
121 if (badNX
|| !pte
.p
) {
123 return pageFault(pte
.p
);
127 entry
.size
= 4 * (1 << 10);
129 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* size
;
134 entry
.size
= 2 * (1 << 20);
135 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
136 entry
.uncacheable
= uncacheable
;
137 entry
.global
= pte
.g
;
138 entry
.patBit
= bits(pte
, 12);
139 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
140 tlb
->insert(entry
.vaddr
, entry
);
145 DPRINTF(PageTableWalker
,
146 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
149 entry
.writable
= entry
.writable
&& pte
.w
;
150 entry
.user
= entry
.user
&& pte
.u
;
151 if (badNX
|| !pte
.p
) {
153 return pageFault(pte
.p
);
155 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
156 entry
.uncacheable
= uncacheable
;
157 entry
.global
= pte
.g
;
158 entry
.patBit
= bits(pte
, 12);
159 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
160 tlb
->insert(entry
.vaddr
, entry
);
164 DPRINTF(PageTableWalker
,
165 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
166 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* size
;
169 return pageFault(pte
.p
);
174 DPRINTF(PageTableWalker
,
175 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
178 entry
.writable
= pte
.w
;
180 if (badNX
|| !pte
.p
) {
182 return pageFault(pte
.p
);
186 entry
.size
= 4 * (1 << 10);
187 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* size
;
192 entry
.size
= 2 * (1 << 20);
193 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
194 entry
.uncacheable
= uncacheable
;
195 entry
.global
= pte
.g
;
196 entry
.patBit
= bits(pte
, 12);
197 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
198 tlb
->insert(entry
.vaddr
, entry
);
203 DPRINTF(PageTableWalker
,
204 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
207 entry
.writable
= entry
.writable
&& pte
.w
;
208 entry
.user
= entry
.user
&& pte
.u
;
209 if (badNX
|| !pte
.p
) {
211 return pageFault(pte
.p
);
213 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
214 entry
.uncacheable
= uncacheable
;
215 entry
.global
= pte
.g
;
216 entry
.patBit
= bits(pte
, 7);
217 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
218 tlb
->insert(entry
.vaddr
, entry
);
222 DPRINTF(PageTableWalker
,
223 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
226 entry
.writable
= pte
.w
;
230 return pageFault(pte
.p
);
234 entry
.size
= 4 * (1 << 10);
236 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* size
;
241 entry
.size
= 4 * (1 << 20);
242 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
243 entry
.uncacheable
= uncacheable
;
244 entry
.global
= pte
.g
;
245 entry
.patBit
= bits(pte
, 12);
246 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
247 tlb
->insert(entry
.vaddr
, entry
);
252 DPRINTF(PageTableWalker
,
253 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
256 entry
.writable
= pte
.w
;
260 return pageFault(pte
.p
);
263 entry
.size
= 4 * (1 << 10);
264 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* size
;
268 DPRINTF(PageTableWalker
,
269 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
272 entry
.writable
= pte
.w
;
276 return pageFault(pte
.p
);
278 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
279 entry
.uncacheable
= uncacheable
;
280 entry
.global
= pte
.g
;
281 entry
.patBit
= bits(pte
, 7);
282 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
283 tlb
->insert(entry
.vaddr
, entry
);
287 panic("Unknown page table walker state %d!\n");
289 PacketPtr oldRead
= read
;
290 //If we didn't return, we're setting up another read.
291 Request::Flags flags
= oldRead
->req
->getFlags();
292 flags
.set(Request::UNCACHEABLE
, uncacheable
);
294 new Request(nextRead
, oldRead
->getSize(), flags
);
295 read
= new Packet(request
, MemCmd::ReadExReq
, Packet::Broadcast
);
297 //If we need to write, adjust the read packet to write the modified value
301 write
->set
<uint64_t>(pte
);
302 write
->cmd
= MemCmd::WriteReq
;
303 write
->setDest(Packet::Broadcast
);
313 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
314 RequestPtr _req
, BaseTLB::Mode _mode
)
316 assert(state
== Ready
);
319 Addr vaddr
= req
->getVaddr();
321 translation
= _translation
;
325 //Figure out what we're doing.
326 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
328 // Check if we're in long mode or not
329 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
334 top
= (cr3
.longPdtb
<< 12) + addr
.longl4
* size
;
337 // We're in some flavor of legacy mode.
338 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
342 top
= (cr3
.paePdtb
<< 5) + addr
.pael3
* size
;
346 top
= (cr3
.pdtb
<< 12) + addr
.norml2
* size
;
351 // Do legacy non PSE.
361 Request::Flags flags
= Request::PHYSICAL
;
363 flags
.set(Request::UNCACHEABLE
);
364 RequestPtr request
= new Request(top
, size
, flags
);
365 read
= new Packet(request
, MemCmd::ReadExReq
, Packet::Broadcast
);
367 Enums::MemoryMode memMode
= sys
->getMemoryMode();
368 if (memMode
== Enums::timing
) {
371 timingFault
= NoFault
;
373 } else if (memMode
== Enums::atomic
) {
376 port
.sendAtomic(read
);
377 PacketPtr write
= NULL
;
378 fault
= doNext(write
);
379 assert(fault
== NoFault
|| read
== NULL
);
383 port
.sendAtomic(write
);
389 panic("Unrecognized memory system mode.\n");
395 Walker::WalkerPort::recvTiming(PacketPtr pkt
)
397 return walker
->recvTiming(pkt
);
401 Walker::recvTiming(PacketPtr pkt
)
403 if (pkt
->isResponse() && !pkt
->wasNacked()) {
405 assert(state
== Waiting
);
411 PacketPtr write
= NULL
;
413 timingFault
= doNext(write
);
415 assert(timingFault
== NoFault
|| read
== NULL
);
417 writes
.push_back(write
);
423 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
426 if (timingFault
== NoFault
) {
428 * Finish the translation. Now that we now the right entry is
429 * in the TLB, this should work with no memory accesses.
430 * There could be new faults unrelated to the table walk like
431 * permissions violations, so we'll need the return value as
434 bool delayedResponse
;
435 Fault fault
= tlb
->translate(req
, tc
, NULL
, mode
,
436 delayedResponse
, true);
437 assert(!delayedResponse
);
438 // Let the CPU continue.
439 translation
->finish(fault
, req
, tc
, mode
);
441 // There was a fault during the walk. Let the CPU know.
442 translation
->finish(timingFault
, req
, tc
, mode
);
445 } else if (pkt
->wasNacked()) {
447 if (!port
.sendTiming(pkt
)) {
450 if (pkt
->isWrite()) {
451 writes
.push_back(pkt
);
462 Walker::WalkerPort::recvAtomic(PacketPtr pkt
)
468 Walker::WalkerPort::recvFunctional(PacketPtr pkt
)
474 Walker::WalkerPort::recvStatusChange(Status status
)
476 if (status
== RangeChange
) {
477 if (!snoopRangeSent
) {
478 snoopRangeSent
= true;
479 sendStatusChange(Port::RangeChange
);
484 panic("Unexpected recvStatusChange.\n");
488 Walker::WalkerPort::recvRetry()
501 Walker::sendPackets()
503 //If we're already waiting for the port to become available, just return.
507 //Reads always have priority
509 PacketPtr pkt
= read
;
512 if (!port
.sendTiming(pkt
)) {
519 //Send off as many of the writes as we can.
520 while (writes
.size()) {
521 PacketPtr write
= writes
.back();
524 if (!port
.sendTiming(write
)) {
526 writes
.push_back(write
);
534 Walker::getPort(const std::string
&if_name
, int idx
)
536 if (if_name
== "port")
539 panic("No page table walker port named %s!\n", if_name
);
543 Walker::pageFault(bool present
)
545 DPRINTF(PageTableWalker
, "Raising page fault.\n");
546 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
547 if (mode
== BaseTLB::Execute
&& !enableNX
)
548 mode
= BaseTLB::Read
;
549 return new PageFault(entry
.vaddr
, present
, mode
, m5reg
.cpl
== 3, false);
555 X86PagetableWalkerParams::create()
557 return new X86ISA::Walker(this);