2 * Copyright (c) 2007 The Hewlett-Packard Development Company
5 * Redistribution and use of this software in source and binary forms,
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58 #include "arch/x86/pagetable.hh"
59 #include "arch/x86/pagetable_walker.hh"
60 #include "arch/x86/tlb.hh"
61 #include "base/bitfield.hh"
62 #include "cpu/thread_context.hh"
63 #include "cpu/base.hh"
64 #include "mem/packet_access.hh"
65 #include "mem/request.hh"
66 #include "sim/system.hh"
70 // Unfortunately, the placement of the base field in a page table entry is
71 // very erratic and would make a mess here. It might be moved here at some
72 // point in the future.
73 BitUnion64(PageTableEntry
)
85 EndBitUnion(PageTableEntry
)
88 Walker::doNext(PacketPtr
&write
)
90 assert(state
!= Ready
&& state
!= Waiting
);
94 pte
= read
->get
<uint64_t>();
96 pte
= read
->get
<uint32_t>();
97 VAddr vaddr
= entry
.vaddr
;
98 bool uncacheable
= pte
.pcd
;
100 bool doWrite
= false;
101 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
104 DPRINTF(PageTableWalker
,
105 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
106 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* size
;
109 entry
.writable
= pte
.w
;
111 if (badNX
|| !pte
.p
) {
113 return pageFault(pte
.p
);
115 entry
.noExec
= pte
.nx
;
119 DPRINTF(PageTableWalker
,
120 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
121 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* size
;
124 entry
.writable
= entry
.writable
&& pte
.w
;
125 entry
.user
= entry
.user
&& pte
.u
;
126 if (badNX
|| !pte
.p
) {
128 return pageFault(pte
.p
);
133 DPRINTF(PageTableWalker
,
134 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
137 entry
.writable
= entry
.writable
&& pte
.w
;
138 entry
.user
= entry
.user
&& pte
.u
;
139 if (badNX
|| !pte
.p
) {
141 return pageFault(pte
.p
);
145 entry
.size
= 4 * (1 << 10);
147 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* size
;
152 entry
.size
= 2 * (1 << 20);
153 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
154 entry
.uncacheable
= uncacheable
;
155 entry
.global
= pte
.g
;
156 entry
.patBit
= bits(pte
, 12);
157 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
158 tlb
->insert(entry
.vaddr
, entry
);
163 DPRINTF(PageTableWalker
,
164 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
167 entry
.writable
= entry
.writable
&& pte
.w
;
168 entry
.user
= entry
.user
&& pte
.u
;
169 if (badNX
|| !pte
.p
) {
171 return pageFault(pte
.p
);
173 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
174 entry
.uncacheable
= uncacheable
;
175 entry
.global
= pte
.g
;
176 entry
.patBit
= bits(pte
, 12);
177 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
178 tlb
->insert(entry
.vaddr
, entry
);
182 DPRINTF(PageTableWalker
,
183 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
184 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* size
;
187 return pageFault(pte
.p
);
192 DPRINTF(PageTableWalker
,
193 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
196 entry
.writable
= pte
.w
;
198 if (badNX
|| !pte
.p
) {
200 return pageFault(pte
.p
);
204 entry
.size
= 4 * (1 << 10);
205 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* size
;
210 entry
.size
= 2 * (1 << 20);
211 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
212 entry
.uncacheable
= uncacheable
;
213 entry
.global
= pte
.g
;
214 entry
.patBit
= bits(pte
, 12);
215 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
216 tlb
->insert(entry
.vaddr
, entry
);
221 DPRINTF(PageTableWalker
,
222 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
225 entry
.writable
= entry
.writable
&& pte
.w
;
226 entry
.user
= entry
.user
&& pte
.u
;
227 if (badNX
|| !pte
.p
) {
229 return pageFault(pte
.p
);
231 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
232 entry
.uncacheable
= uncacheable
;
233 entry
.global
= pte
.g
;
234 entry
.patBit
= bits(pte
, 7);
235 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
236 tlb
->insert(entry
.vaddr
, entry
);
240 DPRINTF(PageTableWalker
,
241 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
244 entry
.writable
= pte
.w
;
248 return pageFault(pte
.p
);
252 entry
.size
= 4 * (1 << 10);
254 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* size
;
259 entry
.size
= 4 * (1 << 20);
260 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
261 entry
.uncacheable
= uncacheable
;
262 entry
.global
= pte
.g
;
263 entry
.patBit
= bits(pte
, 12);
264 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
265 tlb
->insert(entry
.vaddr
, entry
);
270 DPRINTF(PageTableWalker
,
271 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
274 entry
.writable
= pte
.w
;
278 return pageFault(pte
.p
);
281 entry
.size
= 4 * (1 << 10);
282 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* size
;
286 DPRINTF(PageTableWalker
,
287 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
290 entry
.writable
= pte
.w
;
294 return pageFault(pte
.p
);
296 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
297 entry
.uncacheable
= uncacheable
;
298 entry
.global
= pte
.g
;
299 entry
.patBit
= bits(pte
, 7);
300 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
301 tlb
->insert(entry
.vaddr
, entry
);
305 panic("Unknown page table walker state %d!\n");
307 PacketPtr oldRead
= read
;
308 //If we didn't return, we're setting up another read.
309 Request::Flags flags
= oldRead
->req
->getFlags();
310 flags
.set(Request::UNCACHEABLE
, uncacheable
);
312 new Request(nextRead
, oldRead
->getSize(), flags
);
313 read
= new Packet(request
, MemCmd::ReadExReq
, Packet::Broadcast
);
315 //If we need to write, adjust the read packet to write the modified value
319 write
->set
<uint64_t>(pte
);
320 write
->cmd
= MemCmd::WriteReq
;
321 write
->setDest(Packet::Broadcast
);
331 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
332 RequestPtr _req
, BaseTLB::Mode _mode
)
334 assert(state
== Ready
);
337 Addr vaddr
= req
->getVaddr();
339 translation
= _translation
;
343 //Figure out what we're doing.
344 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
346 // Check if we're in long mode or not
347 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
352 top
= (cr3
.longPdtb
<< 12) + addr
.longl4
* size
;
355 // We're in some flavor of legacy mode.
356 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
360 top
= (cr3
.paePdtb
<< 5) + addr
.pael3
* size
;
364 top
= (cr3
.pdtb
<< 12) + addr
.norml2
* size
;
369 // Do legacy non PSE.
379 Request::Flags flags
= Request::PHYSICAL
;
381 flags
.set(Request::UNCACHEABLE
);
382 RequestPtr request
= new Request(top
, size
, flags
);
383 read
= new Packet(request
, MemCmd::ReadExReq
, Packet::Broadcast
);
385 Enums::MemoryMode memMode
= sys
->getMemoryMode();
386 if (memMode
== Enums::timing
) {
389 timingFault
= NoFault
;
391 } else if (memMode
== Enums::atomic
) {
394 port
.sendAtomic(read
);
395 PacketPtr write
= NULL
;
396 fault
= doNext(write
);
397 assert(fault
== NoFault
|| read
== NULL
);
401 port
.sendAtomic(write
);
407 panic("Unrecognized memory system mode.\n");
413 Walker::WalkerPort::recvTiming(PacketPtr pkt
)
415 return walker
->recvTiming(pkt
);
419 Walker::recvTiming(PacketPtr pkt
)
421 if (pkt
->isResponse() && !pkt
->wasNacked()) {
423 assert(state
== Waiting
);
429 PacketPtr write
= NULL
;
431 timingFault
= doNext(write
);
433 assert(timingFault
== NoFault
|| read
== NULL
);
435 writes
.push_back(write
);
441 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
444 if (timingFault
== NoFault
) {
446 * Finish the translation. Now that we now the right entry is
447 * in the TLB, this should work with no memory accesses.
448 * There could be new faults unrelated to the table walk like
449 * permissions violations, so we'll need the return value as
452 bool delayedResponse
;
453 Fault fault
= tlb
->translate(req
, tc
, NULL
, mode
,
454 delayedResponse
, true);
455 assert(!delayedResponse
);
456 // Let the CPU continue.
457 translation
->finish(fault
, req
, tc
, mode
);
459 // There was a fault during the walk. Let the CPU know.
460 translation
->finish(timingFault
, req
, tc
, mode
);
463 } else if (pkt
->wasNacked()) {
465 if (!port
.sendTiming(pkt
)) {
468 if (pkt
->isWrite()) {
469 writes
.push_back(pkt
);
480 Walker::WalkerPort::recvAtomic(PacketPtr pkt
)
486 Walker::WalkerPort::recvFunctional(PacketPtr pkt
)
492 Walker::WalkerPort::recvStatusChange(Status status
)
494 if (status
== RangeChange
) {
495 if (!snoopRangeSent
) {
496 snoopRangeSent
= true;
497 sendStatusChange(Port::RangeChange
);
502 panic("Unexpected recvStatusChange.\n");
506 Walker::WalkerPort::recvRetry()
519 Walker::sendPackets()
521 //If we're already waiting for the port to become available, just return.
525 //Reads always have priority
527 PacketPtr pkt
= read
;
530 if (!port
.sendTiming(pkt
)) {
537 //Send off as many of the writes as we can.
538 while (writes
.size()) {
539 PacketPtr write
= writes
.back();
542 if (!port
.sendTiming(write
)) {
544 writes
.push_back(write
);
552 Walker::getPort(const std::string
&if_name
, int idx
)
554 if (if_name
== "port")
557 panic("No page table walker port named %s!\n", if_name
);
561 Walker::pageFault(bool present
)
563 DPRINTF(PageTableWalker
, "Raising page fault.\n");
564 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
565 if (mode
== BaseTLB::Execute
&& !enableNX
)
566 mode
= BaseTLB::Read
;
567 return new PageFault(entry
.vaddr
, present
, mode
, m5reg
.cpl
== 3, false);
573 X86PagetableWalkerParams::create()
575 return new X86ISA::Walker(this);