2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
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27 * modification, are permitted provided that the following conditions are
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30 * redistributions in binary form must reproduce the above copyright
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34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 #include "arch/x86/pagetable.hh"
53 #include "arch/x86/pagetable_walker.hh"
54 #include "arch/x86/tlb.hh"
55 #include "arch/x86/vtophys.hh"
56 #include "base/bitfield.hh"
57 #include "base/trie.hh"
58 #include "cpu/base.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/PageTableWalker.hh"
61 #include "mem/packet_access.hh"
62 #include "mem/request.hh"
66 // Unfortunately, the placement of the base field in a page table entry is
67 // very erratic and would make a mess here. It might be moved here at some
68 // point in the future.
69 BitUnion64(PageTableEntry
)
81 EndBitUnion(PageTableEntry
)
84 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
85 RequestPtr _req
, BaseTLB::Mode _mode
)
87 // TODO: in timing mode, instead of blocking when there are other
88 // outstanding requests, see if this request can be coalesced with
89 // another one (i.e. either coalesce or start walk)
90 WalkerState
* newState
= new WalkerState(this, _translation
, _req
);
91 newState
->initState(_tc
, _mode
, sys
->isTimingMode());
92 if (currStates
.size()) {
93 assert(newState
->isTiming());
94 DPRINTF(PageTableWalker
, "Walks in progress: %d\n", currStates
.size());
95 currStates
.push_back(newState
);
98 currStates
.push_back(newState
);
99 Fault fault
= newState
->startWalk();
100 if (!newState
->isTiming()) {
101 currStates
.pop_front();
109 Walker::startFunctional(ThreadContext
* _tc
, Addr
&addr
, unsigned &logBytes
,
112 funcState
.initState(_tc
, _mode
);
113 return funcState
.startFunctional(addr
, logBytes
);
117 Walker::WalkerPort::recvTimingResp(PacketPtr pkt
)
119 return walker
->recvTimingResp(pkt
);
123 Walker::recvTimingResp(PacketPtr pkt
)
125 WalkerSenderState
* senderState
=
126 dynamic_cast<WalkerSenderState
*>(pkt
->popSenderState());
127 WalkerState
* senderWalk
= senderState
->senderWalk
;
128 bool walkComplete
= senderWalk
->recvPacket(pkt
);
131 std::list
<WalkerState
*>::iterator iter
;
132 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
133 WalkerState
* walkerState
= *(iter
);
134 if (walkerState
== senderWalk
) {
135 iter
= currStates
.erase(iter
);
140 // Since we block requests when another is outstanding, we
141 // need to check if there is a waiting request to be serviced
142 if (currStates
.size()) {
143 WalkerState
* newState
= currStates
.front();
144 if (!newState
->wasStarted())
145 newState
->startWalk();
152 Walker::WalkerPort::recvRetry()
160 std::list
<WalkerState
*>::iterator iter
;
161 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
162 WalkerState
* walkerState
= *(iter
);
163 if (walkerState
->isRetrying()) {
164 walkerState
->retry();
169 bool Walker::sendTiming(WalkerState
* sendingState
, PacketPtr pkt
)
171 pkt
->pushSenderState(new WalkerSenderState(sendingState
));
172 return port
.sendTimingReq(pkt
);
176 Walker::getMasterPort(const std::string
&if_name
, PortID idx
)
178 if (if_name
== "port")
181 return MemObject::getMasterPort(if_name
, idx
);
185 Walker::WalkerState::initState(ThreadContext
* _tc
,
186 BaseTLB::Mode _mode
, bool _isTiming
)
188 assert(state
== Ready
);
196 Walker::WalkerState::startWalk()
198 Fault fault
= NoFault
;
199 assert(started
== false);
201 setupWalk(req
->getVaddr());
205 timingFault
= NoFault
;
209 walker
->port
.sendAtomic(read
);
210 PacketPtr write
= NULL
;
211 fault
= stepWalk(write
);
212 assert(fault
== NoFault
|| read
== NULL
);
216 walker
->port
.sendAtomic(write
);
225 Walker::WalkerState::startFunctional(Addr
&addr
, unsigned &logBytes
)
227 Fault fault
= NoFault
;
228 assert(started
== false);
233 walker
->port
.sendFunctional(read
);
234 // On a functional access (page table lookup), writes should
235 // not happen so this pointer is ignored after stepWalk
236 PacketPtr write
= NULL
;
237 fault
= stepWalk(write
);
238 assert(fault
== NoFault
|| read
== NULL
);
242 logBytes
= entry
.logBytes
;
249 Walker::WalkerState::stepWalk(PacketPtr
&write
)
251 assert(state
!= Ready
&& state
!= Waiting
);
252 Fault fault
= NoFault
;
256 pte
= read
->get
<uint64_t>();
258 pte
= read
->get
<uint32_t>();
259 VAddr vaddr
= entry
.vaddr
;
260 bool uncacheable
= pte
.pcd
;
262 bool doWrite
= false;
263 bool doTLBInsert
= false;
264 bool doEndWalk
= false;
265 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
268 DPRINTF(PageTableWalker
,
269 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
270 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* dataSize
;
273 entry
.writable
= pte
.w
;
275 if (badNX
|| !pte
.p
) {
277 fault
= pageFault(pte
.p
);
280 entry
.noExec
= pte
.nx
;
284 DPRINTF(PageTableWalker
,
285 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
286 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* dataSize
;
289 entry
.writable
= entry
.writable
&& pte
.w
;
290 entry
.user
= entry
.user
&& pte
.u
;
291 if (badNX
|| !pte
.p
) {
293 fault
= pageFault(pte
.p
);
299 DPRINTF(PageTableWalker
,
300 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
303 entry
.writable
= entry
.writable
&& pte
.w
;
304 entry
.user
= entry
.user
&& pte
.u
;
305 if (badNX
|| !pte
.p
) {
307 fault
= pageFault(pte
.p
);
314 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* dataSize
;
320 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
321 entry
.uncacheable
= uncacheable
;
322 entry
.global
= pte
.g
;
323 entry
.patBit
= bits(pte
, 12);
324 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
330 DPRINTF(PageTableWalker
,
331 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
334 entry
.writable
= entry
.writable
&& pte
.w
;
335 entry
.user
= entry
.user
&& pte
.u
;
336 if (badNX
|| !pte
.p
) {
338 fault
= pageFault(pte
.p
);
341 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
342 entry
.uncacheable
= uncacheable
;
343 entry
.global
= pte
.g
;
344 entry
.patBit
= bits(pte
, 12);
345 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
350 DPRINTF(PageTableWalker
,
351 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
352 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* dataSize
;
355 fault
= pageFault(pte
.p
);
361 DPRINTF(PageTableWalker
,
362 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
365 entry
.writable
= pte
.w
;
367 if (badNX
|| !pte
.p
) {
369 fault
= pageFault(pte
.p
);
375 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* dataSize
;
381 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
382 entry
.uncacheable
= uncacheable
;
383 entry
.global
= pte
.g
;
384 entry
.patBit
= bits(pte
, 12);
385 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
391 DPRINTF(PageTableWalker
,
392 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
395 entry
.writable
= entry
.writable
&& pte
.w
;
396 entry
.user
= entry
.user
&& pte
.u
;
397 if (badNX
|| !pte
.p
) {
399 fault
= pageFault(pte
.p
);
402 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
403 entry
.uncacheable
= uncacheable
;
404 entry
.global
= pte
.g
;
405 entry
.patBit
= bits(pte
, 7);
406 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
411 DPRINTF(PageTableWalker
,
412 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
415 entry
.writable
= pte
.w
;
419 fault
= pageFault(pte
.p
);
426 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
432 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
433 entry
.uncacheable
= uncacheable
;
434 entry
.global
= pte
.g
;
435 entry
.patBit
= bits(pte
, 12);
436 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
442 DPRINTF(PageTableWalker
,
443 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
446 entry
.writable
= pte
.w
;
450 fault
= pageFault(pte
.p
);
455 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
459 DPRINTF(PageTableWalker
,
460 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
463 entry
.writable
= pte
.w
;
467 fault
= pageFault(pte
.p
);
470 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
471 entry
.uncacheable
= uncacheable
;
472 entry
.global
= pte
.g
;
473 entry
.patBit
= bits(pte
, 7);
474 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
479 panic("Unknown page table walker state %d!\n");
484 walker
->tlb
->insert(entry
.vaddr
, entry
);
487 PacketPtr oldRead
= read
;
488 //If we didn't return, we're setting up another read.
489 Request::Flags flags
= oldRead
->req
->getFlags();
490 flags
.set(Request::UNCACHEABLE
, uncacheable
);
492 new Request(nextRead
, oldRead
->getSize(), flags
, walker
->masterId
);
493 read
= new Packet(request
, MemCmd::ReadReq
);
495 // If we need to write, adjust the read packet to write the modified
496 // value back to memory.
499 write
->set
<uint64_t>(pte
);
500 write
->cmd
= MemCmd::WriteReq
;
512 Walker::WalkerState::endWalk()
521 Walker::WalkerState::setupWalk(Addr vaddr
)
524 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
525 // Check if we're in long mode or not
526 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
532 topAddr
= (cr3
.longPdtb
<< 12) + addr
.longl4
* dataSize
;
535 // We're in some flavor of legacy mode.
536 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
540 topAddr
= (cr3
.paePdtb
<< 5) + addr
.pael3
* dataSize
;
544 topAddr
= (cr3
.pdtb
<< 12) + addr
.norml2
* dataSize
;
549 // Do legacy non PSE.
559 Request::Flags flags
= Request::PHYSICAL
;
561 flags
.set(Request::UNCACHEABLE
);
562 RequestPtr request
= new Request(topAddr
, dataSize
, flags
,
564 read
= new Packet(request
, MemCmd::ReadReq
);
569 Walker::WalkerState::recvPacket(PacketPtr pkt
)
571 assert(pkt
->isResponse());
573 assert(state
== Waiting
);
579 PacketPtr write
= NULL
;
581 timingFault
= stepWalk(write
);
583 assert(timingFault
== NoFault
|| read
== NULL
);
585 writes
.push_back(write
);
591 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
594 if (timingFault
== NoFault
) {
596 * Finish the translation. Now that we now the right entry is
597 * in the TLB, this should work with no memory accesses.
598 * There could be new faults unrelated to the table walk like
599 * permissions violations, so we'll need the return value as
602 bool delayedResponse
;
603 Fault fault
= walker
->tlb
->translate(req
, tc
, NULL
, mode
,
604 delayedResponse
, true);
605 assert(!delayedResponse
);
606 // Let the CPU continue.
607 translation
->finish(fault
, req
, tc
, mode
);
609 // There was a fault during the walk. Let the CPU know.
610 translation
->finish(timingFault
, req
, tc
, mode
);
619 Walker::WalkerState::sendPackets()
621 //If we're already waiting for the port to become available, just return.
625 //Reads always have priority
627 PacketPtr pkt
= read
;
630 if (!walker
->sendTiming(this, pkt
)) {
637 //Send off as many of the writes as we can.
638 while (writes
.size()) {
639 PacketPtr write
= writes
.back();
642 if (!walker
->sendTiming(this, write
)) {
644 writes
.push_back(write
);
652 Walker::WalkerState::isRetrying()
658 Walker::WalkerState::isTiming()
664 Walker::WalkerState::wasStarted()
670 Walker::WalkerState::retry()
677 Walker::WalkerState::pageFault(bool present
)
679 DPRINTF(PageTableWalker
, "Raising page fault.\n");
680 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
681 if (mode
== BaseTLB::Execute
&& !enableNX
)
682 mode
= BaseTLB::Read
;
683 return new PageFault(entry
.vaddr
, present
, mode
, m5reg
.cpl
== 3, false);
686 /* end namespace X86ISA */ }
689 X86PagetableWalkerParams::create()
691 return new X86ISA::Walker(this);