2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 #include "arch/x86/pagetable.hh"
53 #include "arch/x86/pagetable_walker.hh"
54 #include "arch/x86/tlb.hh"
55 #include "arch/x86/vtophys.hh"
56 #include "base/bitfield.hh"
57 #include "base/trie.hh"
58 #include "cpu/base.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/PageTableWalker.hh"
61 #include "mem/packet_access.hh"
62 #include "mem/request.hh"
67 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
68 RequestPtr _req
, BaseTLB::Mode _mode
)
70 // TODO: in timing mode, instead of blocking when there are other
71 // outstanding requests, see if this request can be coalesced with
72 // another one (i.e. either coalesce or start walk)
73 WalkerState
* newState
= new WalkerState(this, _translation
, _req
);
74 newState
->initState(_tc
, _mode
, sys
->isTimingMode());
75 if (currStates
.size()) {
76 assert(newState
->isTiming());
77 DPRINTF(PageTableWalker
, "Walks in progress: %d\n", currStates
.size());
78 currStates
.push_back(newState
);
81 currStates
.push_back(newState
);
82 Fault fault
= newState
->startWalk();
83 if (!newState
->isTiming()) {
84 currStates
.pop_front();
92 Walker::startFunctional(ThreadContext
* _tc
, Addr
&addr
, unsigned &logBytes
,
95 funcState
.initState(_tc
, _mode
);
96 return funcState
.startFunctional(addr
, logBytes
);
100 Walker::WalkerPort::recvTimingResp(PacketPtr pkt
)
102 return walker
->recvTimingResp(pkt
);
106 Walker::recvTimingResp(PacketPtr pkt
)
108 WalkerSenderState
* senderState
=
109 dynamic_cast<WalkerSenderState
*>(pkt
->popSenderState());
110 WalkerState
* senderWalk
= senderState
->senderWalk
;
111 bool walkComplete
= senderWalk
->recvPacket(pkt
);
114 std::list
<WalkerState
*>::iterator iter
;
115 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
116 WalkerState
* walkerState
= *(iter
);
117 if (walkerState
== senderWalk
) {
118 iter
= currStates
.erase(iter
);
123 // Since we block requests when another is outstanding, we
124 // need to check if there is a waiting request to be serviced
125 if (currStates
.size())
132 Walker::WalkerPort::recvRetry()
140 std::list
<WalkerState
*>::iterator iter
;
141 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
142 WalkerState
* walkerState
= *(iter
);
143 if (walkerState
->isRetrying()) {
144 walkerState
->retry();
149 bool Walker::sendTiming(WalkerState
* sendingState
, PacketPtr pkt
)
151 WalkerSenderState
* walker_state
= new WalkerSenderState(sendingState
);
152 pkt
->pushSenderState(walker_state
);
153 if (port
.sendTimingReq(pkt
)) {
156 // undo the adding of the sender state and delete it, as we
157 // will do it again the next time we attempt to send it
158 pkt
->popSenderState();
166 Walker::getMasterPort(const std::string
&if_name
, PortID idx
)
168 if (if_name
== "port")
171 return MemObject::getMasterPort(if_name
, idx
);
175 Walker::WalkerState::initState(ThreadContext
* _tc
,
176 BaseTLB::Mode _mode
, bool _isTiming
)
178 assert(state
== Ready
);
186 Walker::startWalkWrapper()
188 unsigned num_squashed
= 0;
189 WalkerState
*currState
= currStates
.front();
190 while ((num_squashed
< numSquashable
) && currState
&&
191 currState
->translation
->squashed()) {
192 currStates
.pop_front();
195 DPRINTF(PageTableWalker
, "Squashing table walk for address %#x\n",
196 currState
->req
->getVaddr());
198 // finish the translation which will delete the translation object
199 currState
->translation
->finish(new UnimpFault("Squashed Inst"),
200 currState
->req
, currState
->tc
, currState
->mode
);
202 // delete the current request
205 // check the next translation request, if it exists
206 if (currStates
.size())
207 currState
= currStates
.front();
211 if (currState
&& !currState
->wasStarted())
212 currState
->startWalk();
216 Walker::WalkerState::startWalk()
218 Fault fault
= NoFault
;
221 setupWalk(req
->getVaddr());
225 timingFault
= NoFault
;
229 walker
->port
.sendAtomic(read
);
230 PacketPtr write
= NULL
;
231 fault
= stepWalk(write
);
232 assert(fault
== NoFault
|| read
== NULL
);
236 walker
->port
.sendAtomic(write
);
245 Walker::WalkerState::startFunctional(Addr
&addr
, unsigned &logBytes
)
247 Fault fault
= NoFault
;
253 walker
->port
.sendFunctional(read
);
254 // On a functional access (page table lookup), writes should
255 // not happen so this pointer is ignored after stepWalk
256 PacketPtr write
= NULL
;
257 fault
= stepWalk(write
);
258 assert(fault
== NoFault
|| read
== NULL
);
262 logBytes
= entry
.logBytes
;
269 Walker::WalkerState::stepWalk(PacketPtr
&write
)
271 assert(state
!= Ready
&& state
!= Waiting
);
272 Fault fault
= NoFault
;
276 pte
= read
->get
<uint64_t>();
278 pte
= read
->get
<uint32_t>();
279 VAddr vaddr
= entry
.vaddr
;
280 bool uncacheable
= pte
.pcd
;
282 bool doWrite
= false;
283 bool doTLBInsert
= false;
284 bool doEndWalk
= false;
285 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
288 DPRINTF(PageTableWalker
,
289 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
290 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* dataSize
;
293 entry
.writable
= pte
.w
;
295 if (badNX
|| !pte
.p
) {
297 fault
= pageFault(pte
.p
);
300 entry
.noExec
= pte
.nx
;
304 DPRINTF(PageTableWalker
,
305 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
306 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* dataSize
;
309 entry
.writable
= entry
.writable
&& pte
.w
;
310 entry
.user
= entry
.user
&& pte
.u
;
311 if (badNX
|| !pte
.p
) {
313 fault
= pageFault(pte
.p
);
319 DPRINTF(PageTableWalker
,
320 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
323 entry
.writable
= entry
.writable
&& pte
.w
;
324 entry
.user
= entry
.user
&& pte
.u
;
325 if (badNX
|| !pte
.p
) {
327 fault
= pageFault(pte
.p
);
334 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* dataSize
;
340 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
341 entry
.uncacheable
= uncacheable
;
342 entry
.global
= pte
.g
;
343 entry
.patBit
= bits(pte
, 12);
344 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
350 DPRINTF(PageTableWalker
,
351 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
354 entry
.writable
= entry
.writable
&& pte
.w
;
355 entry
.user
= entry
.user
&& pte
.u
;
356 if (badNX
|| !pte
.p
) {
358 fault
= pageFault(pte
.p
);
361 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
362 entry
.uncacheable
= uncacheable
;
363 entry
.global
= pte
.g
;
364 entry
.patBit
= bits(pte
, 12);
365 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
370 DPRINTF(PageTableWalker
,
371 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
372 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* dataSize
;
375 fault
= pageFault(pte
.p
);
381 DPRINTF(PageTableWalker
,
382 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
385 entry
.writable
= pte
.w
;
387 if (badNX
|| !pte
.p
) {
389 fault
= pageFault(pte
.p
);
395 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* dataSize
;
401 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
402 entry
.uncacheable
= uncacheable
;
403 entry
.global
= pte
.g
;
404 entry
.patBit
= bits(pte
, 12);
405 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
411 DPRINTF(PageTableWalker
,
412 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
415 entry
.writable
= entry
.writable
&& pte
.w
;
416 entry
.user
= entry
.user
&& pte
.u
;
417 if (badNX
|| !pte
.p
) {
419 fault
= pageFault(pte
.p
);
422 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
423 entry
.uncacheable
= uncacheable
;
424 entry
.global
= pte
.g
;
425 entry
.patBit
= bits(pte
, 7);
426 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
431 DPRINTF(PageTableWalker
,
432 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
435 entry
.writable
= pte
.w
;
439 fault
= pageFault(pte
.p
);
446 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
452 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
453 entry
.uncacheable
= uncacheable
;
454 entry
.global
= pte
.g
;
455 entry
.patBit
= bits(pte
, 12);
456 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
462 DPRINTF(PageTableWalker
,
463 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
466 entry
.writable
= pte
.w
;
470 fault
= pageFault(pte
.p
);
475 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
479 DPRINTF(PageTableWalker
,
480 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
483 entry
.writable
= pte
.w
;
487 fault
= pageFault(pte
.p
);
490 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
491 entry
.uncacheable
= uncacheable
;
492 entry
.global
= pte
.g
;
493 entry
.patBit
= bits(pte
, 7);
494 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
499 panic("Unknown page table walker state %d!\n");
504 walker
->tlb
->insert(entry
.vaddr
, entry
);
507 PacketPtr oldRead
= read
;
508 //If we didn't return, we're setting up another read.
509 Request::Flags flags
= oldRead
->req
->getFlags();
510 flags
.set(Request::UNCACHEABLE
, uncacheable
);
512 new Request(nextRead
, oldRead
->getSize(), flags
, walker
->masterId
);
513 read
= new Packet(request
, MemCmd::ReadReq
);
515 // If we need to write, adjust the read packet to write the modified
516 // value back to memory.
519 write
->set
<uint64_t>(pte
);
520 write
->cmd
= MemCmd::WriteReq
;
532 Walker::WalkerState::endWalk()
541 Walker::WalkerState::setupWalk(Addr vaddr
)
544 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
545 // Check if we're in long mode or not
546 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
552 topAddr
= (cr3
.longPdtb
<< 12) + addr
.longl4
* dataSize
;
555 // We're in some flavor of legacy mode.
556 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
560 topAddr
= (cr3
.paePdtb
<< 5) + addr
.pael3
* dataSize
;
564 topAddr
= (cr3
.pdtb
<< 12) + addr
.norml2
* dataSize
;
569 // Do legacy non PSE.
579 Request::Flags flags
= Request::PHYSICAL
;
581 flags
.set(Request::UNCACHEABLE
);
582 RequestPtr request
= new Request(topAddr
, dataSize
, flags
,
584 read
= new Packet(request
, MemCmd::ReadReq
);
589 Walker::WalkerState::recvPacket(PacketPtr pkt
)
591 assert(pkt
->isResponse());
593 assert(state
== Waiting
);
596 // should not have a pending read it we also had one outstanding
599 // @todo someone should pay for this
600 pkt
->firstWordDelay
= pkt
->lastWordDelay
= 0;
604 PacketPtr write
= NULL
;
606 timingFault
= stepWalk(write
);
608 assert(timingFault
== NoFault
|| read
== NULL
);
610 writes
.push_back(write
);
616 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
619 if (timingFault
== NoFault
) {
621 * Finish the translation. Now that we now the right entry is
622 * in the TLB, this should work with no memory accesses.
623 * There could be new faults unrelated to the table walk like
624 * permissions violations, so we'll need the return value as
627 bool delayedResponse
;
628 Fault fault
= walker
->tlb
->translate(req
, tc
, NULL
, mode
,
629 delayedResponse
, true);
630 assert(!delayedResponse
);
631 // Let the CPU continue.
632 translation
->finish(fault
, req
, tc
, mode
);
634 // There was a fault during the walk. Let the CPU know.
635 translation
->finish(timingFault
, req
, tc
, mode
);
644 Walker::WalkerState::sendPackets()
646 //If we're already waiting for the port to become available, just return.
650 //Reads always have priority
652 PacketPtr pkt
= read
;
655 if (!walker
->sendTiming(this, pkt
)) {
662 //Send off as many of the writes as we can.
663 while (writes
.size()) {
664 PacketPtr write
= writes
.back();
667 if (!walker
->sendTiming(this, write
)) {
669 writes
.push_back(write
);
677 Walker::WalkerState::isRetrying()
683 Walker::WalkerState::isTiming()
689 Walker::WalkerState::wasStarted()
695 Walker::WalkerState::retry()
702 Walker::WalkerState::pageFault(bool present
)
704 DPRINTF(PageTableWalker
, "Raising page fault.\n");
705 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
706 if (mode
== BaseTLB::Execute
&& !enableNX
)
707 mode
= BaseTLB::Read
;
708 return new PageFault(entry
.vaddr
, present
, mode
, m5reg
.cpl
== 3, false);
711 /* end namespace X86ISA */ }
714 X86PagetableWalkerParams::create()
716 return new X86ISA::Walker(this);