2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
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27 * modification, are permitted provided that the following conditions are
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30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
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33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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52 #include "arch/x86/pagetable.hh"
53 #include "arch/x86/pagetable_walker.hh"
54 #include "arch/x86/tlb.hh"
55 #include "arch/x86/vtophys.hh"
56 #include "base/bitfield.hh"
57 #include "base/trie.hh"
58 #include "cpu/base.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/PageTableWalker.hh"
61 #include "mem/packet_access.hh"
62 #include "mem/request.hh"
66 // Unfortunately, the placement of the base field in a page table entry is
67 // very erratic and would make a mess here. It might be moved here at some
68 // point in the future.
69 BitUnion64(PageTableEntry
)
81 EndBitUnion(PageTableEntry
)
84 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
85 RequestPtr _req
, BaseTLB::Mode _mode
)
87 // TODO: in timing mode, instead of blocking when there are other
88 // outstanding requests, see if this request can be coalesced with
89 // another one (i.e. either coalesce or start walk)
90 WalkerState
* newState
= new WalkerState(this, _translation
, _req
);
91 newState
->initState(_tc
, _mode
, sys
->isTimingMode());
92 if (currStates
.size()) {
93 assert(newState
->isTiming());
94 DPRINTF(PageTableWalker
, "Walks in progress: %d\n", currStates
.size());
95 currStates
.push_back(newState
);
98 currStates
.push_back(newState
);
99 Fault fault
= newState
->startWalk();
100 if (!newState
->isTiming()) {
101 currStates
.pop_front();
109 Walker::startFunctional(ThreadContext
* _tc
, Addr
&addr
, unsigned &logBytes
,
112 funcState
.initState(_tc
, _mode
);
113 return funcState
.startFunctional(addr
, logBytes
);
117 Walker::WalkerPort::recvTimingResp(PacketPtr pkt
)
119 return walker
->recvTimingResp(pkt
);
123 Walker::recvTimingResp(PacketPtr pkt
)
125 WalkerSenderState
* senderState
=
126 dynamic_cast<WalkerSenderState
*>(pkt
->popSenderState());
127 WalkerState
* senderWalk
= senderState
->senderWalk
;
128 bool walkComplete
= senderWalk
->recvPacket(pkt
);
131 std::list
<WalkerState
*>::iterator iter
;
132 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
133 WalkerState
* walkerState
= *(iter
);
134 if (walkerState
== senderWalk
) {
135 iter
= currStates
.erase(iter
);
140 // Since we block requests when another is outstanding, we
141 // need to check if there is a waiting request to be serviced
142 if (currStates
.size())
149 Walker::WalkerPort::recvRetry()
157 std::list
<WalkerState
*>::iterator iter
;
158 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
159 WalkerState
* walkerState
= *(iter
);
160 if (walkerState
->isRetrying()) {
161 walkerState
->retry();
166 bool Walker::sendTiming(WalkerState
* sendingState
, PacketPtr pkt
)
168 pkt
->pushSenderState(new WalkerSenderState(sendingState
));
169 return port
.sendTimingReq(pkt
);
173 Walker::getMasterPort(const std::string
&if_name
, PortID idx
)
175 if (if_name
== "port")
178 return MemObject::getMasterPort(if_name
, idx
);
182 Walker::WalkerState::initState(ThreadContext
* _tc
,
183 BaseTLB::Mode _mode
, bool _isTiming
)
185 assert(state
== Ready
);
193 Walker::startWalkWrapper()
195 unsigned num_squashed
= 0;
196 WalkerState
*currState
= currStates
.front();
197 while ((num_squashed
< numSquashable
) && currState
&&
198 currState
->translation
->squashed()) {
199 currStates
.pop_front();
202 DPRINTF(PageTableWalker
, "Squashing table walk for address %#x\n",
203 currState
->req
->getVaddr());
205 // finish the translation which will delete the translation object
206 currState
->translation
->finish(new UnimpFault("Squashed Inst"),
207 currState
->req
, currState
->tc
, currState
->mode
);
209 // delete the current request
212 // check the next translation request, if it exists
213 if (currStates
.size())
214 currState
= currStates
.front();
218 if (currState
&& !currState
->wasStarted())
219 currState
->startWalk();
223 Walker::WalkerState::startWalk()
225 Fault fault
= NoFault
;
226 assert(started
== false);
228 setupWalk(req
->getVaddr());
232 timingFault
= NoFault
;
236 walker
->port
.sendAtomic(read
);
237 PacketPtr write
= NULL
;
238 fault
= stepWalk(write
);
239 assert(fault
== NoFault
|| read
== NULL
);
243 walker
->port
.sendAtomic(write
);
252 Walker::WalkerState::startFunctional(Addr
&addr
, unsigned &logBytes
)
254 Fault fault
= NoFault
;
255 assert(started
== false);
260 walker
->port
.sendFunctional(read
);
261 // On a functional access (page table lookup), writes should
262 // not happen so this pointer is ignored after stepWalk
263 PacketPtr write
= NULL
;
264 fault
= stepWalk(write
);
265 assert(fault
== NoFault
|| read
== NULL
);
269 logBytes
= entry
.logBytes
;
276 Walker::WalkerState::stepWalk(PacketPtr
&write
)
278 assert(state
!= Ready
&& state
!= Waiting
);
279 Fault fault
= NoFault
;
283 pte
= read
->get
<uint64_t>();
285 pte
= read
->get
<uint32_t>();
286 VAddr vaddr
= entry
.vaddr
;
287 bool uncacheable
= pte
.pcd
;
289 bool doWrite
= false;
290 bool doTLBInsert
= false;
291 bool doEndWalk
= false;
292 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
295 DPRINTF(PageTableWalker
,
296 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
297 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* dataSize
;
300 entry
.writable
= pte
.w
;
302 if (badNX
|| !pte
.p
) {
304 fault
= pageFault(pte
.p
);
307 entry
.noExec
= pte
.nx
;
311 DPRINTF(PageTableWalker
,
312 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
313 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* dataSize
;
316 entry
.writable
= entry
.writable
&& pte
.w
;
317 entry
.user
= entry
.user
&& pte
.u
;
318 if (badNX
|| !pte
.p
) {
320 fault
= pageFault(pte
.p
);
326 DPRINTF(PageTableWalker
,
327 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
330 entry
.writable
= entry
.writable
&& pte
.w
;
331 entry
.user
= entry
.user
&& pte
.u
;
332 if (badNX
|| !pte
.p
) {
334 fault
= pageFault(pte
.p
);
341 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* dataSize
;
347 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
348 entry
.uncacheable
= uncacheable
;
349 entry
.global
= pte
.g
;
350 entry
.patBit
= bits(pte
, 12);
351 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
357 DPRINTF(PageTableWalker
,
358 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
361 entry
.writable
= entry
.writable
&& pte
.w
;
362 entry
.user
= entry
.user
&& pte
.u
;
363 if (badNX
|| !pte
.p
) {
365 fault
= pageFault(pte
.p
);
368 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
369 entry
.uncacheable
= uncacheable
;
370 entry
.global
= pte
.g
;
371 entry
.patBit
= bits(pte
, 12);
372 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
377 DPRINTF(PageTableWalker
,
378 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
379 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* dataSize
;
382 fault
= pageFault(pte
.p
);
388 DPRINTF(PageTableWalker
,
389 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
392 entry
.writable
= pte
.w
;
394 if (badNX
|| !pte
.p
) {
396 fault
= pageFault(pte
.p
);
402 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* dataSize
;
408 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
409 entry
.uncacheable
= uncacheable
;
410 entry
.global
= pte
.g
;
411 entry
.patBit
= bits(pte
, 12);
412 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
418 DPRINTF(PageTableWalker
,
419 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
422 entry
.writable
= entry
.writable
&& pte
.w
;
423 entry
.user
= entry
.user
&& pte
.u
;
424 if (badNX
|| !pte
.p
) {
426 fault
= pageFault(pte
.p
);
429 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
430 entry
.uncacheable
= uncacheable
;
431 entry
.global
= pte
.g
;
432 entry
.patBit
= bits(pte
, 7);
433 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
438 DPRINTF(PageTableWalker
,
439 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
442 entry
.writable
= pte
.w
;
446 fault
= pageFault(pte
.p
);
453 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
459 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
460 entry
.uncacheable
= uncacheable
;
461 entry
.global
= pte
.g
;
462 entry
.patBit
= bits(pte
, 12);
463 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
469 DPRINTF(PageTableWalker
,
470 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
473 entry
.writable
= pte
.w
;
477 fault
= pageFault(pte
.p
);
482 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
486 DPRINTF(PageTableWalker
,
487 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
490 entry
.writable
= pte
.w
;
494 fault
= pageFault(pte
.p
);
497 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
498 entry
.uncacheable
= uncacheable
;
499 entry
.global
= pte
.g
;
500 entry
.patBit
= bits(pte
, 7);
501 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
506 panic("Unknown page table walker state %d!\n");
511 walker
->tlb
->insert(entry
.vaddr
, entry
);
514 PacketPtr oldRead
= read
;
515 //If we didn't return, we're setting up another read.
516 Request::Flags flags
= oldRead
->req
->getFlags();
517 flags
.set(Request::UNCACHEABLE
, uncacheable
);
519 new Request(nextRead
, oldRead
->getSize(), flags
, walker
->masterId
);
520 read
= new Packet(request
, MemCmd::ReadReq
);
522 // If we need to write, adjust the read packet to write the modified
523 // value back to memory.
526 write
->set
<uint64_t>(pte
);
527 write
->cmd
= MemCmd::WriteReq
;
539 Walker::WalkerState::endWalk()
548 Walker::WalkerState::setupWalk(Addr vaddr
)
551 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
552 // Check if we're in long mode or not
553 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
559 topAddr
= (cr3
.longPdtb
<< 12) + addr
.longl4
* dataSize
;
562 // We're in some flavor of legacy mode.
563 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
567 topAddr
= (cr3
.paePdtb
<< 5) + addr
.pael3
* dataSize
;
571 topAddr
= (cr3
.pdtb
<< 12) + addr
.norml2
* dataSize
;
576 // Do legacy non PSE.
586 Request::Flags flags
= Request::PHYSICAL
;
588 flags
.set(Request::UNCACHEABLE
);
589 RequestPtr request
= new Request(topAddr
, dataSize
, flags
,
591 read
= new Packet(request
, MemCmd::ReadReq
);
596 Walker::WalkerState::recvPacket(PacketPtr pkt
)
598 assert(pkt
->isResponse());
600 assert(state
== Waiting
);
604 // @todo someone should pay for this
605 pkt
->busFirstWordDelay
= pkt
->busLastWordDelay
= 0;
609 PacketPtr write
= NULL
;
611 timingFault
= stepWalk(write
);
613 assert(timingFault
== NoFault
|| read
== NULL
);
615 writes
.push_back(write
);
621 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
624 if (timingFault
== NoFault
) {
626 * Finish the translation. Now that we now the right entry is
627 * in the TLB, this should work with no memory accesses.
628 * There could be new faults unrelated to the table walk like
629 * permissions violations, so we'll need the return value as
632 bool delayedResponse
;
633 Fault fault
= walker
->tlb
->translate(req
, tc
, NULL
, mode
,
634 delayedResponse
, true);
635 assert(!delayedResponse
);
636 // Let the CPU continue.
637 translation
->finish(fault
, req
, tc
, mode
);
639 // There was a fault during the walk. Let the CPU know.
640 translation
->finish(timingFault
, req
, tc
, mode
);
649 Walker::WalkerState::sendPackets()
651 //If we're already waiting for the port to become available, just return.
655 //Reads always have priority
657 PacketPtr pkt
= read
;
660 if (!walker
->sendTiming(this, pkt
)) {
667 //Send off as many of the writes as we can.
668 while (writes
.size()) {
669 PacketPtr write
= writes
.back();
672 if (!walker
->sendTiming(this, write
)) {
674 writes
.push_back(write
);
682 Walker::WalkerState::isRetrying()
688 Walker::WalkerState::isTiming()
694 Walker::WalkerState::wasStarted()
700 Walker::WalkerState::retry()
707 Walker::WalkerState::pageFault(bool present
)
709 DPRINTF(PageTableWalker
, "Raising page fault.\n");
710 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
711 if (mode
== BaseTLB::Execute
&& !enableNX
)
712 mode
= BaseTLB::Read
;
713 return new PageFault(entry
.vaddr
, present
, mode
, m5reg
.cpl
== 3, false);
716 /* end namespace X86ISA */ }
719 X86PagetableWalkerParams::create()
721 return new X86ISA::Walker(this);