2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 #include "arch/x86/pagetable_walker.hh"
56 #include "arch/x86/pagetable.hh"
57 #include "arch/x86/tlb.hh"
58 #include "arch/x86/vtophys.hh"
59 #include "base/bitfield.hh"
60 #include "base/trie.hh"
61 #include "cpu/base.hh"
62 #include "cpu/thread_context.hh"
63 #include "debug/PageTableWalker.hh"
64 #include "mem/packet_access.hh"
65 #include "mem/request.hh"
70 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
71 const RequestPtr
&_req
, BaseTLB::Mode _mode
)
73 // TODO: in timing mode, instead of blocking when there are other
74 // outstanding requests, see if this request can be coalesced with
75 // another one (i.e. either coalesce or start walk)
76 WalkerState
* newState
= new WalkerState(this, _translation
, _req
);
77 newState
->initState(_tc
, _mode
, sys
->isTimingMode());
78 if (currStates
.size()) {
79 assert(newState
->isTiming());
80 DPRINTF(PageTableWalker
, "Walks in progress: %d\n", currStates
.size());
81 currStates
.push_back(newState
);
84 currStates
.push_back(newState
);
85 Fault fault
= newState
->startWalk();
86 if (!newState
->isTiming()) {
87 currStates
.pop_front();
95 Walker::startFunctional(ThreadContext
* _tc
, Addr
&addr
, unsigned &logBytes
,
98 funcState
.initState(_tc
, _mode
);
99 return funcState
.startFunctional(addr
, logBytes
);
103 Walker::WalkerPort::recvTimingResp(PacketPtr pkt
)
105 return walker
->recvTimingResp(pkt
);
109 Walker::recvTimingResp(PacketPtr pkt
)
111 WalkerSenderState
* senderState
=
112 dynamic_cast<WalkerSenderState
*>(pkt
->popSenderState());
113 WalkerState
* senderWalk
= senderState
->senderWalk
;
114 bool walkComplete
= senderWalk
->recvPacket(pkt
);
117 std::list
<WalkerState
*>::iterator iter
;
118 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
119 WalkerState
* walkerState
= *(iter
);
120 if (walkerState
== senderWalk
) {
121 iter
= currStates
.erase(iter
);
126 // Since we block requests when another is outstanding, we
127 // need to check if there is a waiting request to be serviced
128 if (currStates
.size() && !startWalkWrapperEvent
.scheduled())
129 // delay sending any new requests until we are finished
130 // with the responses
131 schedule(startWalkWrapperEvent
, clockEdge());
137 Walker::WalkerPort::recvReqRetry()
139 walker
->recvReqRetry();
143 Walker::recvReqRetry()
145 std::list
<WalkerState
*>::iterator iter
;
146 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
147 WalkerState
* walkerState
= *(iter
);
148 if (walkerState
->isRetrying()) {
149 walkerState
->retry();
154 bool Walker::sendTiming(WalkerState
* sendingState
, PacketPtr pkt
)
156 WalkerSenderState
* walker_state
= new WalkerSenderState(sendingState
);
157 pkt
->pushSenderState(walker_state
);
158 if (port
.sendTimingReq(pkt
)) {
161 // undo the adding of the sender state and delete it, as we
162 // will do it again the next time we attempt to send it
163 pkt
->popSenderState();
171 Walker::getMasterPort(const std::string
&if_name
, PortID idx
)
173 if (if_name
== "port")
176 return MemObject::getMasterPort(if_name
, idx
);
180 Walker::WalkerState::initState(ThreadContext
* _tc
,
181 BaseTLB::Mode _mode
, bool _isTiming
)
183 assert(state
== Ready
);
191 Walker::startWalkWrapper()
193 unsigned num_squashed
= 0;
194 WalkerState
*currState
= currStates
.front();
195 while ((num_squashed
< numSquashable
) && currState
&&
196 currState
->translation
->squashed()) {
197 currStates
.pop_front();
200 DPRINTF(PageTableWalker
, "Squashing table walk for address %#x\n",
201 currState
->req
->getVaddr());
203 // finish the translation which will delete the translation object
204 currState
->translation
->finish(
205 std::make_shared
<UnimpFault
>("Squashed Inst"),
206 currState
->req
, currState
->tc
, currState
->mode
);
208 // delete the current request
211 // check the next translation request, if it exists
212 if (currStates
.size())
213 currState
= currStates
.front();
217 if (currState
&& !currState
->wasStarted())
218 currState
->startWalk();
222 Walker::WalkerState::startWalk()
224 Fault fault
= NoFault
;
227 setupWalk(req
->getVaddr());
231 timingFault
= NoFault
;
235 walker
->port
.sendAtomic(read
);
236 PacketPtr write
= NULL
;
237 fault
= stepWalk(write
);
238 assert(fault
== NoFault
|| read
== NULL
);
242 walker
->port
.sendAtomic(write
);
251 Walker::WalkerState::startFunctional(Addr
&addr
, unsigned &logBytes
)
253 Fault fault
= NoFault
;
259 walker
->port
.sendFunctional(read
);
260 // On a functional access (page table lookup), writes should
261 // not happen so this pointer is ignored after stepWalk
262 PacketPtr write
= NULL
;
263 fault
= stepWalk(write
);
264 assert(fault
== NoFault
|| read
== NULL
);
268 logBytes
= entry
.logBytes
;
275 Walker::WalkerState::stepWalk(PacketPtr
&write
)
277 assert(state
!= Ready
&& state
!= Waiting
);
278 Fault fault
= NoFault
;
282 pte
= read
->getLE
<uint64_t>();
284 pte
= read
->getLE
<uint32_t>();
285 VAddr vaddr
= entry
.vaddr
;
286 bool uncacheable
= pte
.pcd
;
288 bool doWrite
= false;
289 bool doTLBInsert
= false;
290 bool doEndWalk
= false;
291 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
294 DPRINTF(PageTableWalker
,
295 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
296 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* dataSize
;
299 entry
.writable
= pte
.w
;
301 if (badNX
|| !pte
.p
) {
303 fault
= pageFault(pte
.p
);
306 entry
.noExec
= pte
.nx
;
310 DPRINTF(PageTableWalker
,
311 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
312 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* dataSize
;
315 entry
.writable
= entry
.writable
&& pte
.w
;
316 entry
.user
= entry
.user
&& pte
.u
;
317 if (badNX
|| !pte
.p
) {
319 fault
= pageFault(pte
.p
);
325 DPRINTF(PageTableWalker
,
326 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
329 entry
.writable
= entry
.writable
&& pte
.w
;
330 entry
.user
= entry
.user
&& pte
.u
;
331 if (badNX
|| !pte
.p
) {
333 fault
= pageFault(pte
.p
);
340 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* dataSize
;
346 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
347 entry
.uncacheable
= uncacheable
;
348 entry
.global
= pte
.g
;
349 entry
.patBit
= bits(pte
, 12);
350 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
356 DPRINTF(PageTableWalker
,
357 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
360 entry
.writable
= entry
.writable
&& pte
.w
;
361 entry
.user
= entry
.user
&& pte
.u
;
362 if (badNX
|| !pte
.p
) {
364 fault
= pageFault(pte
.p
);
367 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
368 entry
.uncacheable
= uncacheable
;
369 entry
.global
= pte
.g
;
370 entry
.patBit
= bits(pte
, 12);
371 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
376 DPRINTF(PageTableWalker
,
377 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
378 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* dataSize
;
381 fault
= pageFault(pte
.p
);
387 DPRINTF(PageTableWalker
,
388 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
391 entry
.writable
= pte
.w
;
393 if (badNX
|| !pte
.p
) {
395 fault
= pageFault(pte
.p
);
401 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* dataSize
;
407 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
408 entry
.uncacheable
= uncacheable
;
409 entry
.global
= pte
.g
;
410 entry
.patBit
= bits(pte
, 12);
411 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
417 DPRINTF(PageTableWalker
,
418 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
421 entry
.writable
= entry
.writable
&& pte
.w
;
422 entry
.user
= entry
.user
&& pte
.u
;
423 if (badNX
|| !pte
.p
) {
425 fault
= pageFault(pte
.p
);
428 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
429 entry
.uncacheable
= uncacheable
;
430 entry
.global
= pte
.g
;
431 entry
.patBit
= bits(pte
, 7);
432 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
437 DPRINTF(PageTableWalker
,
438 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
441 entry
.writable
= pte
.w
;
445 fault
= pageFault(pte
.p
);
452 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
458 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
459 entry
.uncacheable
= uncacheable
;
460 entry
.global
= pte
.g
;
461 entry
.patBit
= bits(pte
, 12);
462 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
468 DPRINTF(PageTableWalker
,
469 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
472 entry
.writable
= pte
.w
;
476 fault
= pageFault(pte
.p
);
481 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
485 DPRINTF(PageTableWalker
,
486 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
489 entry
.writable
= pte
.w
;
493 fault
= pageFault(pte
.p
);
496 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
497 entry
.uncacheable
= uncacheable
;
498 entry
.global
= pte
.g
;
499 entry
.patBit
= bits(pte
, 7);
500 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
505 panic("Unknown page table walker state %d!\n");
510 walker
->tlb
->insert(entry
.vaddr
, entry
);
513 PacketPtr oldRead
= read
;
514 //If we didn't return, we're setting up another read.
515 Request::Flags flags
= oldRead
->req
->getFlags();
516 flags
.set(Request::UNCACHEABLE
, uncacheable
);
517 RequestPtr request
= std::make_shared
<Request
>(
518 nextRead
, oldRead
->getSize(), flags
, walker
->masterId
);
519 read
= new Packet(request
, MemCmd::ReadReq
);
521 // If we need to write, adjust the read packet to write the modified
522 // value back to memory.
525 write
->setLE
<uint64_t>(pte
);
526 write
->cmd
= MemCmd::WriteReq
;
536 Walker::WalkerState::endWalk()
544 Walker::WalkerState::setupWalk(Addr vaddr
)
547 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
548 // Check if we're in long mode or not
549 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
555 topAddr
= (cr3
.longPdtb
<< 12) + addr
.longl4
* dataSize
;
558 // We're in some flavor of legacy mode.
559 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
563 topAddr
= (cr3
.paePdtb
<< 5) + addr
.pael3
* dataSize
;
567 topAddr
= (cr3
.pdtb
<< 12) + addr
.norml2
* dataSize
;
572 // Do legacy non PSE.
582 Request::Flags flags
= Request::PHYSICAL
;
584 flags
.set(Request::UNCACHEABLE
);
586 RequestPtr request
= std::make_shared
<Request
>(
587 topAddr
, dataSize
, flags
, walker
->masterId
);
589 read
= new Packet(request
, MemCmd::ReadReq
);
594 Walker::WalkerState::recvPacket(PacketPtr pkt
)
596 assert(pkt
->isResponse());
598 assert(state
== Waiting
);
601 // should not have a pending read it we also had one outstanding
604 // @todo someone should pay for this
605 pkt
->headerDelay
= pkt
->payloadDelay
= 0;
609 PacketPtr write
= NULL
;
611 timingFault
= stepWalk(write
);
613 assert(timingFault
== NoFault
|| read
== NULL
);
615 writes
.push_back(write
);
621 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
624 if (timingFault
== NoFault
) {
626 * Finish the translation. Now that we know the right entry is
627 * in the TLB, this should work with no memory accesses.
628 * There could be new faults unrelated to the table walk like
629 * permissions violations, so we'll need the return value as
632 bool delayedResponse
;
633 Fault fault
= walker
->tlb
->translate(req
, tc
, NULL
, mode
,
634 delayedResponse
, true);
635 assert(!delayedResponse
);
636 // Let the CPU continue.
637 translation
->finish(fault
, req
, tc
, mode
);
639 // There was a fault during the walk. Let the CPU know.
640 translation
->finish(timingFault
, req
, tc
, mode
);
649 Walker::WalkerState::sendPackets()
651 //If we're already waiting for the port to become available, just return.
655 //Reads always have priority
657 PacketPtr pkt
= read
;
660 if (!walker
->sendTiming(this, pkt
)) {
667 //Send off as many of the writes as we can.
668 while (writes
.size()) {
669 PacketPtr write
= writes
.back();
672 if (!walker
->sendTiming(this, write
)) {
674 writes
.push_back(write
);
682 Walker::WalkerState::isRetrying()
688 Walker::WalkerState::isTiming()
694 Walker::WalkerState::wasStarted()
700 Walker::WalkerState::retry()
707 Walker::WalkerState::pageFault(bool present
)
709 DPRINTF(PageTableWalker
, "Raising page fault.\n");
710 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
711 if (mode
== BaseTLB::Execute
&& !enableNX
)
712 mode
= BaseTLB::Read
;
713 return std::make_shared
<PageFault
>(entry
.vaddr
, present
, mode
,
714 m5reg
.cpl
== 3, false);
717 /* end namespace X86ISA */ }
720 X86PagetableWalkerParams::create()
722 return new X86ISA::Walker(this);