2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 #include "arch/x86/pagetable.hh"
53 #include "arch/x86/pagetable_walker.hh"
54 #include "arch/x86/tlb.hh"
55 #include "arch/x86/vtophys.hh"
56 #include "base/bitfield.hh"
57 #include "base/trie.hh"
58 #include "cpu/base.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/PageTableWalker.hh"
61 #include "mem/packet_access.hh"
62 #include "mem/request.hh"
66 // Unfortunately, the placement of the base field in a page table entry is
67 // very erratic and would make a mess here. It might be moved here at some
68 // point in the future.
69 BitUnion64(PageTableEntry
)
81 EndBitUnion(PageTableEntry
)
84 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
85 RequestPtr _req
, BaseTLB::Mode _mode
)
87 // TODO: in timing mode, instead of blocking when there are other
88 // outstanding requests, see if this request can be coalesced with
89 // another one (i.e. either coalesce or start walk)
90 WalkerState
* newState
= new WalkerState(this, _translation
, _req
);
91 newState
->initState(_tc
, _mode
, sys
->isTimingMode());
92 if (currStates
.size()) {
93 assert(newState
->isTiming());
94 DPRINTF(PageTableWalker
, "Walks in progress: %d\n", currStates
.size());
95 currStates
.push_back(newState
);
98 currStates
.push_back(newState
);
99 Fault fault
= newState
->startWalk();
100 if (!newState
->isTiming()) {
101 currStates
.pop_front();
109 Walker::startFunctional(ThreadContext
* _tc
, Addr
&addr
, unsigned &logBytes
,
112 funcState
.initState(_tc
, _mode
);
113 return funcState
.startFunctional(addr
, logBytes
);
117 Walker::WalkerPort::recvTimingResp(PacketPtr pkt
)
119 return walker
->recvTimingResp(pkt
);
123 Walker::recvTimingResp(PacketPtr pkt
)
125 WalkerSenderState
* senderState
=
126 dynamic_cast<WalkerSenderState
*>(pkt
->popSenderState());
127 WalkerState
* senderWalk
= senderState
->senderWalk
;
128 bool walkComplete
= senderWalk
->recvPacket(pkt
);
131 std::list
<WalkerState
*>::iterator iter
;
132 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
133 WalkerState
* walkerState
= *(iter
);
134 if (walkerState
== senderWalk
) {
135 iter
= currStates
.erase(iter
);
140 // Since we block requests when another is outstanding, we
141 // need to check if there is a waiting request to be serviced
142 if (currStates
.size())
149 Walker::WalkerPort::recvRetry()
157 std::list
<WalkerState
*>::iterator iter
;
158 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
159 WalkerState
* walkerState
= *(iter
);
160 if (walkerState
->isRetrying()) {
161 walkerState
->retry();
166 bool Walker::sendTiming(WalkerState
* sendingState
, PacketPtr pkt
)
168 WalkerSenderState
* walker_state
= new WalkerSenderState(sendingState
);
169 pkt
->pushSenderState(walker_state
);
170 if (port
.sendTimingReq(pkt
)) {
173 // undo the adding of the sender state and delete it, as we
174 // will do it again the next time we attempt to send it
175 pkt
->popSenderState();
183 Walker::getMasterPort(const std::string
&if_name
, PortID idx
)
185 if (if_name
== "port")
188 return MemObject::getMasterPort(if_name
, idx
);
192 Walker::WalkerState::initState(ThreadContext
* _tc
,
193 BaseTLB::Mode _mode
, bool _isTiming
)
195 assert(state
== Ready
);
203 Walker::startWalkWrapper()
205 unsigned num_squashed
= 0;
206 WalkerState
*currState
= currStates
.front();
207 while ((num_squashed
< numSquashable
) && currState
&&
208 currState
->translation
->squashed()) {
209 currStates
.pop_front();
212 DPRINTF(PageTableWalker
, "Squashing table walk for address %#x\n",
213 currState
->req
->getVaddr());
215 // finish the translation which will delete the translation object
216 currState
->translation
->finish(new UnimpFault("Squashed Inst"),
217 currState
->req
, currState
->tc
, currState
->mode
);
219 // delete the current request
222 // check the next translation request, if it exists
223 if (currStates
.size())
224 currState
= currStates
.front();
228 if (currState
&& !currState
->wasStarted())
229 currState
->startWalk();
233 Walker::WalkerState::startWalk()
235 Fault fault
= NoFault
;
238 setupWalk(req
->getVaddr());
242 timingFault
= NoFault
;
246 walker
->port
.sendAtomic(read
);
247 PacketPtr write
= NULL
;
248 fault
= stepWalk(write
);
249 assert(fault
== NoFault
|| read
== NULL
);
253 walker
->port
.sendAtomic(write
);
262 Walker::WalkerState::startFunctional(Addr
&addr
, unsigned &logBytes
)
264 Fault fault
= NoFault
;
270 walker
->port
.sendFunctional(read
);
271 // On a functional access (page table lookup), writes should
272 // not happen so this pointer is ignored after stepWalk
273 PacketPtr write
= NULL
;
274 fault
= stepWalk(write
);
275 assert(fault
== NoFault
|| read
== NULL
);
279 logBytes
= entry
.logBytes
;
286 Walker::WalkerState::stepWalk(PacketPtr
&write
)
288 assert(state
!= Ready
&& state
!= Waiting
);
289 Fault fault
= NoFault
;
293 pte
= read
->get
<uint64_t>();
295 pte
= read
->get
<uint32_t>();
296 VAddr vaddr
= entry
.vaddr
;
297 bool uncacheable
= pte
.pcd
;
299 bool doWrite
= false;
300 bool doTLBInsert
= false;
301 bool doEndWalk
= false;
302 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
305 DPRINTF(PageTableWalker
,
306 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
307 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* dataSize
;
310 entry
.writable
= pte
.w
;
312 if (badNX
|| !pte
.p
) {
314 fault
= pageFault(pte
.p
);
317 entry
.noExec
= pte
.nx
;
321 DPRINTF(PageTableWalker
,
322 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
323 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* dataSize
;
326 entry
.writable
= entry
.writable
&& pte
.w
;
327 entry
.user
= entry
.user
&& pte
.u
;
328 if (badNX
|| !pte
.p
) {
330 fault
= pageFault(pte
.p
);
336 DPRINTF(PageTableWalker
,
337 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
340 entry
.writable
= entry
.writable
&& pte
.w
;
341 entry
.user
= entry
.user
&& pte
.u
;
342 if (badNX
|| !pte
.p
) {
344 fault
= pageFault(pte
.p
);
351 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* dataSize
;
357 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
358 entry
.uncacheable
= uncacheable
;
359 entry
.global
= pte
.g
;
360 entry
.patBit
= bits(pte
, 12);
361 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
367 DPRINTF(PageTableWalker
,
368 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
371 entry
.writable
= entry
.writable
&& pte
.w
;
372 entry
.user
= entry
.user
&& pte
.u
;
373 if (badNX
|| !pte
.p
) {
375 fault
= pageFault(pte
.p
);
378 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
379 entry
.uncacheable
= uncacheable
;
380 entry
.global
= pte
.g
;
381 entry
.patBit
= bits(pte
, 12);
382 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
387 DPRINTF(PageTableWalker
,
388 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
389 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* dataSize
;
392 fault
= pageFault(pte
.p
);
398 DPRINTF(PageTableWalker
,
399 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
402 entry
.writable
= pte
.w
;
404 if (badNX
|| !pte
.p
) {
406 fault
= pageFault(pte
.p
);
412 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* dataSize
;
418 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
419 entry
.uncacheable
= uncacheable
;
420 entry
.global
= pte
.g
;
421 entry
.patBit
= bits(pte
, 12);
422 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
428 DPRINTF(PageTableWalker
,
429 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
432 entry
.writable
= entry
.writable
&& pte
.w
;
433 entry
.user
= entry
.user
&& pte
.u
;
434 if (badNX
|| !pte
.p
) {
436 fault
= pageFault(pte
.p
);
439 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
440 entry
.uncacheable
= uncacheable
;
441 entry
.global
= pte
.g
;
442 entry
.patBit
= bits(pte
, 7);
443 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
448 DPRINTF(PageTableWalker
,
449 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
452 entry
.writable
= pte
.w
;
456 fault
= pageFault(pte
.p
);
463 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
469 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
470 entry
.uncacheable
= uncacheable
;
471 entry
.global
= pte
.g
;
472 entry
.patBit
= bits(pte
, 12);
473 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
479 DPRINTF(PageTableWalker
,
480 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
483 entry
.writable
= pte
.w
;
487 fault
= pageFault(pte
.p
);
492 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
496 DPRINTF(PageTableWalker
,
497 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
500 entry
.writable
= pte
.w
;
504 fault
= pageFault(pte
.p
);
507 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
508 entry
.uncacheable
= uncacheable
;
509 entry
.global
= pte
.g
;
510 entry
.patBit
= bits(pte
, 7);
511 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
516 panic("Unknown page table walker state %d!\n");
521 walker
->tlb
->insert(entry
.vaddr
, entry
);
524 PacketPtr oldRead
= read
;
525 //If we didn't return, we're setting up another read.
526 Request::Flags flags
= oldRead
->req
->getFlags();
527 flags
.set(Request::UNCACHEABLE
, uncacheable
);
529 new Request(nextRead
, oldRead
->getSize(), flags
, walker
->masterId
);
530 read
= new Packet(request
, MemCmd::ReadReq
);
532 // If we need to write, adjust the read packet to write the modified
533 // value back to memory.
536 write
->set
<uint64_t>(pte
);
537 write
->cmd
= MemCmd::WriteReq
;
549 Walker::WalkerState::endWalk()
558 Walker::WalkerState::setupWalk(Addr vaddr
)
561 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
562 // Check if we're in long mode or not
563 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
569 topAddr
= (cr3
.longPdtb
<< 12) + addr
.longl4
* dataSize
;
572 // We're in some flavor of legacy mode.
573 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
577 topAddr
= (cr3
.paePdtb
<< 5) + addr
.pael3
* dataSize
;
581 topAddr
= (cr3
.pdtb
<< 12) + addr
.norml2
* dataSize
;
586 // Do legacy non PSE.
596 Request::Flags flags
= Request::PHYSICAL
;
598 flags
.set(Request::UNCACHEABLE
);
599 RequestPtr request
= new Request(topAddr
, dataSize
, flags
,
601 read
= new Packet(request
, MemCmd::ReadReq
);
606 Walker::WalkerState::recvPacket(PacketPtr pkt
)
608 assert(pkt
->isResponse());
610 assert(state
== Waiting
);
613 // should not have a pending read it we also had one outstanding
616 // @todo someone should pay for this
617 pkt
->busFirstWordDelay
= pkt
->busLastWordDelay
= 0;
621 PacketPtr write
= NULL
;
623 timingFault
= stepWalk(write
);
625 assert(timingFault
== NoFault
|| read
== NULL
);
627 writes
.push_back(write
);
633 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
636 if (timingFault
== NoFault
) {
638 * Finish the translation. Now that we now the right entry is
639 * in the TLB, this should work with no memory accesses.
640 * There could be new faults unrelated to the table walk like
641 * permissions violations, so we'll need the return value as
644 bool delayedResponse
;
645 Fault fault
= walker
->tlb
->translate(req
, tc
, NULL
, mode
,
646 delayedResponse
, true);
647 assert(!delayedResponse
);
648 // Let the CPU continue.
649 translation
->finish(fault
, req
, tc
, mode
);
651 // There was a fault during the walk. Let the CPU know.
652 translation
->finish(timingFault
, req
, tc
, mode
);
661 Walker::WalkerState::sendPackets()
663 //If we're already waiting for the port to become available, just return.
667 //Reads always have priority
669 PacketPtr pkt
= read
;
672 if (!walker
->sendTiming(this, pkt
)) {
679 //Send off as many of the writes as we can.
680 while (writes
.size()) {
681 PacketPtr write
= writes
.back();
684 if (!walker
->sendTiming(this, write
)) {
686 writes
.push_back(write
);
694 Walker::WalkerState::isRetrying()
700 Walker::WalkerState::isTiming()
706 Walker::WalkerState::wasStarted()
712 Walker::WalkerState::retry()
719 Walker::WalkerState::pageFault(bool present
)
721 DPRINTF(PageTableWalker
, "Raising page fault.\n");
722 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
723 if (mode
== BaseTLB::Execute
&& !enableNX
)
724 mode
= BaseTLB::Read
;
725 return new PageFault(entry
.vaddr
, present
, mode
, m5reg
.cpl
== 3, false);
728 /* end namespace X86ISA */ }
731 X86PagetableWalkerParams::create()
733 return new X86ISA::Walker(this);