2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
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35 * this software without specific prior written permission.
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52 #include "arch/x86/pagetable.hh"
53 #include "arch/x86/pagetable_walker.hh"
54 #include "arch/x86/tlb.hh"
55 #include "arch/x86/vtophys.hh"
56 #include "base/bitfield.hh"
57 #include "base/trie.hh"
58 #include "cpu/base.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/PageTableWalker.hh"
61 #include "mem/packet_access.hh"
62 #include "mem/request.hh"
66 // Unfortunately, the placement of the base field in a page table entry is
67 // very erratic and would make a mess here. It might be moved here at some
68 // point in the future.
69 BitUnion64(PageTableEntry
)
81 EndBitUnion(PageTableEntry
)
84 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
85 RequestPtr _req
, BaseTLB::Mode _mode
)
87 // TODO: in timing mode, instead of blocking when there are other
88 // outstanding requests, see if this request can be coalesced with
89 // another one (i.e. either coalesce or start walk)
90 WalkerState
* newState
= new WalkerState(this, _translation
, _req
);
91 newState
->initState(_tc
, _mode
, sys
->getMemoryMode() == Enums::timing
);
92 if (currStates
.size()) {
93 assert(newState
->isTiming());
94 DPRINTF(PageTableWalker
, "Walks in progress: %d\n", currStates
.size());
95 currStates
.push_back(newState
);
98 currStates
.push_back(newState
);
99 Fault fault
= newState
->startWalk();
100 if (!newState
->isTiming()) {
101 currStates
.pop_front();
109 Walker::startFunctional(ThreadContext
* _tc
, Addr
&addr
, unsigned &logBytes
,
112 funcState
.initState(_tc
, _mode
);
113 return funcState
.startFunctional(addr
, logBytes
);
117 Walker::WalkerPort::recvTimingResp(PacketPtr pkt
)
119 return walker
->recvTimingResp(pkt
);
123 Walker::recvTimingResp(PacketPtr pkt
)
125 WalkerSenderState
* senderState
=
126 dynamic_cast<WalkerSenderState
*>(pkt
->senderState
);
127 pkt
->senderState
= senderState
->saved
;
128 WalkerState
* senderWalk
= senderState
->senderWalk
;
129 bool walkComplete
= senderWalk
->recvPacket(pkt
);
132 std::list
<WalkerState
*>::iterator iter
;
133 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
134 WalkerState
* walkerState
= *(iter
);
135 if (walkerState
== senderWalk
) {
136 iter
= currStates
.erase(iter
);
141 // Since we block requests when another is outstanding, we
142 // need to check if there is a waiting request to be serviced
143 if (currStates
.size()) {
144 WalkerState
* newState
= currStates
.front();
145 if (!newState
->wasStarted())
146 newState
->startWalk();
153 Walker::WalkerPort::recvRetry()
161 std::list
<WalkerState
*>::iterator iter
;
162 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
163 WalkerState
* walkerState
= *(iter
);
164 if (walkerState
->isRetrying()) {
165 walkerState
->retry();
170 bool Walker::sendTiming(WalkerState
* sendingState
, PacketPtr pkt
)
172 pkt
->senderState
= new WalkerSenderState(sendingState
, pkt
->senderState
);
173 return port
.sendTimingReq(pkt
);
177 Walker::getMasterPort(const std::string
&if_name
, int idx
)
179 if (if_name
== "port")
182 return MemObject::getMasterPort(if_name
, idx
);
186 Walker::WalkerState::initState(ThreadContext
* _tc
,
187 BaseTLB::Mode _mode
, bool _isTiming
)
189 assert(state
== Ready
);
197 Walker::WalkerState::startWalk()
199 Fault fault
= NoFault
;
200 assert(started
== false);
202 setupWalk(req
->getVaddr());
206 timingFault
= NoFault
;
210 walker
->port
.sendAtomic(read
);
211 PacketPtr write
= NULL
;
212 fault
= stepWalk(write
);
213 assert(fault
== NoFault
|| read
== NULL
);
217 walker
->port
.sendAtomic(write
);
226 Walker::WalkerState::startFunctional(Addr
&addr
, unsigned &logBytes
)
228 Fault fault
= NoFault
;
229 assert(started
== false);
234 walker
->port
.sendFunctional(read
);
235 // On a functional access (page table lookup), writes should
236 // not happen so this pointer is ignored after stepWalk
237 PacketPtr write
= NULL
;
238 fault
= stepWalk(write
);
239 assert(fault
== NoFault
|| read
== NULL
);
243 logBytes
= entry
.logBytes
;
250 Walker::WalkerState::stepWalk(PacketPtr
&write
)
252 assert(state
!= Ready
&& state
!= Waiting
);
253 Fault fault
= NoFault
;
257 pte
= read
->get
<uint64_t>();
259 pte
= read
->get
<uint32_t>();
260 VAddr vaddr
= entry
.vaddr
;
261 bool uncacheable
= pte
.pcd
;
263 bool doWrite
= false;
264 bool doTLBInsert
= false;
265 bool doEndWalk
= false;
266 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
269 DPRINTF(PageTableWalker
,
270 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
271 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* dataSize
;
274 entry
.writable
= pte
.w
;
276 if (badNX
|| !pte
.p
) {
278 fault
= pageFault(pte
.p
);
281 entry
.noExec
= pte
.nx
;
285 DPRINTF(PageTableWalker
,
286 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
287 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* dataSize
;
290 entry
.writable
= entry
.writable
&& pte
.w
;
291 entry
.user
= entry
.user
&& pte
.u
;
292 if (badNX
|| !pte
.p
) {
294 fault
= pageFault(pte
.p
);
300 DPRINTF(PageTableWalker
,
301 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
304 entry
.writable
= entry
.writable
&& pte
.w
;
305 entry
.user
= entry
.user
&& pte
.u
;
306 if (badNX
|| !pte
.p
) {
308 fault
= pageFault(pte
.p
);
315 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* dataSize
;
321 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
322 entry
.uncacheable
= uncacheable
;
323 entry
.global
= pte
.g
;
324 entry
.patBit
= bits(pte
, 12);
325 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
331 DPRINTF(PageTableWalker
,
332 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
335 entry
.writable
= entry
.writable
&& pte
.w
;
336 entry
.user
= entry
.user
&& pte
.u
;
337 if (badNX
|| !pte
.p
) {
339 fault
= pageFault(pte
.p
);
342 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
343 entry
.uncacheable
= uncacheable
;
344 entry
.global
= pte
.g
;
345 entry
.patBit
= bits(pte
, 12);
346 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
351 DPRINTF(PageTableWalker
,
352 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
353 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* dataSize
;
356 fault
= pageFault(pte
.p
);
362 DPRINTF(PageTableWalker
,
363 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
366 entry
.writable
= pte
.w
;
368 if (badNX
|| !pte
.p
) {
370 fault
= pageFault(pte
.p
);
376 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* dataSize
;
382 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
383 entry
.uncacheable
= uncacheable
;
384 entry
.global
= pte
.g
;
385 entry
.patBit
= bits(pte
, 12);
386 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
392 DPRINTF(PageTableWalker
,
393 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
396 entry
.writable
= entry
.writable
&& pte
.w
;
397 entry
.user
= entry
.user
&& pte
.u
;
398 if (badNX
|| !pte
.p
) {
400 fault
= pageFault(pte
.p
);
403 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
404 entry
.uncacheable
= uncacheable
;
405 entry
.global
= pte
.g
;
406 entry
.patBit
= bits(pte
, 7);
407 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
412 DPRINTF(PageTableWalker
,
413 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
416 entry
.writable
= pte
.w
;
420 fault
= pageFault(pte
.p
);
427 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
433 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
434 entry
.uncacheable
= uncacheable
;
435 entry
.global
= pte
.g
;
436 entry
.patBit
= bits(pte
, 12);
437 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
443 DPRINTF(PageTableWalker
,
444 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
447 entry
.writable
= pte
.w
;
451 fault
= pageFault(pte
.p
);
456 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
460 DPRINTF(PageTableWalker
,
461 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
464 entry
.writable
= pte
.w
;
468 fault
= pageFault(pte
.p
);
471 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
472 entry
.uncacheable
= uncacheable
;
473 entry
.global
= pte
.g
;
474 entry
.patBit
= bits(pte
, 7);
475 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
480 panic("Unknown page table walker state %d!\n");
485 walker
->tlb
->insert(entry
.vaddr
, entry
);
488 PacketPtr oldRead
= read
;
489 //If we didn't return, we're setting up another read.
490 Request::Flags flags
= oldRead
->req
->getFlags();
491 flags
.set(Request::UNCACHEABLE
, uncacheable
);
493 new Request(nextRead
, oldRead
->getSize(), flags
, walker
->masterId
);
494 read
= new Packet(request
, MemCmd::ReadReq
);
496 // If we need to write, adjust the read packet to write the modified
497 // value back to memory.
500 write
->set
<uint64_t>(pte
);
501 write
->cmd
= MemCmd::WriteReq
;
513 Walker::WalkerState::endWalk()
522 Walker::WalkerState::setupWalk(Addr vaddr
)
525 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
526 // Check if we're in long mode or not
527 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
533 topAddr
= (cr3
.longPdtb
<< 12) + addr
.longl4
* dataSize
;
536 // We're in some flavor of legacy mode.
537 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
541 topAddr
= (cr3
.paePdtb
<< 5) + addr
.pael3
* dataSize
;
545 topAddr
= (cr3
.pdtb
<< 12) + addr
.norml2
* dataSize
;
550 // Do legacy non PSE.
560 Request::Flags flags
= Request::PHYSICAL
;
562 flags
.set(Request::UNCACHEABLE
);
563 RequestPtr request
= new Request(topAddr
, dataSize
, flags
,
565 read
= new Packet(request
, MemCmd::ReadReq
);
570 Walker::WalkerState::recvPacket(PacketPtr pkt
)
572 assert(pkt
->isResponse());
574 assert(state
== Waiting
);
580 PacketPtr write
= NULL
;
582 timingFault
= stepWalk(write
);
584 assert(timingFault
== NoFault
|| read
== NULL
);
586 writes
.push_back(write
);
592 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
595 if (timingFault
== NoFault
) {
597 * Finish the translation. Now that we now the right entry is
598 * in the TLB, this should work with no memory accesses.
599 * There could be new faults unrelated to the table walk like
600 * permissions violations, so we'll need the return value as
603 bool delayedResponse
;
604 Fault fault
= walker
->tlb
->translate(req
, tc
, NULL
, mode
,
605 delayedResponse
, true);
606 assert(!delayedResponse
);
607 // Let the CPU continue.
608 translation
->finish(fault
, req
, tc
, mode
);
610 // There was a fault during the walk. Let the CPU know.
611 translation
->finish(timingFault
, req
, tc
, mode
);
620 Walker::WalkerState::sendPackets()
622 //If we're already waiting for the port to become available, just return.
626 //Reads always have priority
628 PacketPtr pkt
= read
;
631 if (!walker
->sendTiming(this, pkt
)) {
638 //Send off as many of the writes as we can.
639 while (writes
.size()) {
640 PacketPtr write
= writes
.back();
643 if (!walker
->sendTiming(this, write
)) {
645 writes
.push_back(write
);
653 Walker::WalkerState::isRetrying()
659 Walker::WalkerState::isTiming()
665 Walker::WalkerState::wasStarted()
671 Walker::WalkerState::retry()
678 Walker::WalkerState::pageFault(bool present
)
680 DPRINTF(PageTableWalker
, "Raising page fault.\n");
681 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
682 if (mode
== BaseTLB::Execute
&& !enableNX
)
683 mode
= BaseTLB::Read
;
684 return new PageFault(entry
.vaddr
, present
, mode
, m5reg
.cpl
== 3, false);
687 /* end namespace X86ISA */ }
690 X86PagetableWalkerParams::create()
692 return new X86ISA::Walker(this);