2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 #include "arch/x86/pagetable.hh"
55 #include "arch/x86/pagetable_walker.hh"
56 #include "arch/x86/tlb.hh"
57 #include "arch/x86/vtophys.hh"
58 #include "base/bitfield.hh"
59 #include "base/trie.hh"
60 #include "cpu/base.hh"
61 #include "cpu/thread_context.hh"
62 #include "debug/PageTableWalker.hh"
63 #include "mem/packet_access.hh"
64 #include "mem/request.hh"
69 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
70 RequestPtr _req
, BaseTLB::Mode _mode
)
72 // TODO: in timing mode, instead of blocking when there are other
73 // outstanding requests, see if this request can be coalesced with
74 // another one (i.e. either coalesce or start walk)
75 WalkerState
* newState
= new WalkerState(this, _translation
, _req
);
76 newState
->initState(_tc
, _mode
, sys
->isTimingMode());
77 if (currStates
.size()) {
78 assert(newState
->isTiming());
79 DPRINTF(PageTableWalker
, "Walks in progress: %d\n", currStates
.size());
80 currStates
.push_back(newState
);
83 currStates
.push_back(newState
);
84 Fault fault
= newState
->startWalk();
85 if (!newState
->isTiming()) {
86 currStates
.pop_front();
94 Walker::startFunctional(ThreadContext
* _tc
, Addr
&addr
, unsigned &logBytes
,
97 funcState
.initState(_tc
, _mode
);
98 return funcState
.startFunctional(addr
, logBytes
);
102 Walker::WalkerPort::recvTimingResp(PacketPtr pkt
)
104 return walker
->recvTimingResp(pkt
);
108 Walker::recvTimingResp(PacketPtr pkt
)
110 WalkerSenderState
* senderState
=
111 dynamic_cast<WalkerSenderState
*>(pkt
->popSenderState());
112 WalkerState
* senderWalk
= senderState
->senderWalk
;
113 bool walkComplete
= senderWalk
->recvPacket(pkt
);
116 std::list
<WalkerState
*>::iterator iter
;
117 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
118 WalkerState
* walkerState
= *(iter
);
119 if (walkerState
== senderWalk
) {
120 iter
= currStates
.erase(iter
);
125 // Since we block requests when another is outstanding, we
126 // need to check if there is a waiting request to be serviced
127 if (currStates
.size() && !startWalkWrapperEvent
.scheduled())
128 // delay sending any new requests until we are finished
129 // with the responses
130 schedule(startWalkWrapperEvent
, clockEdge());
136 Walker::WalkerPort::recvRetry()
144 std::list
<WalkerState
*>::iterator iter
;
145 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
146 WalkerState
* walkerState
= *(iter
);
147 if (walkerState
->isRetrying()) {
148 walkerState
->retry();
153 bool Walker::sendTiming(WalkerState
* sendingState
, PacketPtr pkt
)
155 WalkerSenderState
* walker_state
= new WalkerSenderState(sendingState
);
156 pkt
->pushSenderState(walker_state
);
157 if (port
.sendTimingReq(pkt
)) {
160 // undo the adding of the sender state and delete it, as we
161 // will do it again the next time we attempt to send it
162 pkt
->popSenderState();
170 Walker::getMasterPort(const std::string
&if_name
, PortID idx
)
172 if (if_name
== "port")
175 return MemObject::getMasterPort(if_name
, idx
);
179 Walker::WalkerState::initState(ThreadContext
* _tc
,
180 BaseTLB::Mode _mode
, bool _isTiming
)
182 assert(state
== Ready
);
190 Walker::startWalkWrapper()
192 unsigned num_squashed
= 0;
193 WalkerState
*currState
= currStates
.front();
194 while ((num_squashed
< numSquashable
) && currState
&&
195 currState
->translation
->squashed()) {
196 currStates
.pop_front();
199 DPRINTF(PageTableWalker
, "Squashing table walk for address %#x\n",
200 currState
->req
->getVaddr());
202 // finish the translation which will delete the translation object
203 currState
->translation
->finish(
204 std::make_shared
<UnimpFault
>("Squashed Inst"),
205 currState
->req
, currState
->tc
, currState
->mode
);
207 // delete the current request
210 // check the next translation request, if it exists
211 if (currStates
.size())
212 currState
= currStates
.front();
216 if (currState
&& !currState
->wasStarted())
217 currState
->startWalk();
221 Walker::WalkerState::startWalk()
223 Fault fault
= NoFault
;
226 setupWalk(req
->getVaddr());
230 timingFault
= NoFault
;
234 walker
->port
.sendAtomic(read
);
235 PacketPtr write
= NULL
;
236 fault
= stepWalk(write
);
237 assert(fault
== NoFault
|| read
== NULL
);
241 walker
->port
.sendAtomic(write
);
250 Walker::WalkerState::startFunctional(Addr
&addr
, unsigned &logBytes
)
252 Fault fault
= NoFault
;
258 walker
->port
.sendFunctional(read
);
259 // On a functional access (page table lookup), writes should
260 // not happen so this pointer is ignored after stepWalk
261 PacketPtr write
= NULL
;
262 fault
= stepWalk(write
);
263 assert(fault
== NoFault
|| read
== NULL
);
267 logBytes
= entry
.logBytes
;
274 Walker::WalkerState::stepWalk(PacketPtr
&write
)
276 assert(state
!= Ready
&& state
!= Waiting
);
277 Fault fault
= NoFault
;
281 pte
= read
->get
<uint64_t>();
283 pte
= read
->get
<uint32_t>();
284 VAddr vaddr
= entry
.vaddr
;
285 bool uncacheable
= pte
.pcd
;
287 bool doWrite
= false;
288 bool doTLBInsert
= false;
289 bool doEndWalk
= false;
290 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
293 DPRINTF(PageTableWalker
,
294 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
295 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* dataSize
;
298 entry
.writable
= pte
.w
;
300 if (badNX
|| !pte
.p
) {
302 fault
= pageFault(pte
.p
);
305 entry
.noExec
= pte
.nx
;
309 DPRINTF(PageTableWalker
,
310 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
311 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* dataSize
;
314 entry
.writable
= entry
.writable
&& pte
.w
;
315 entry
.user
= entry
.user
&& pte
.u
;
316 if (badNX
|| !pte
.p
) {
318 fault
= pageFault(pte
.p
);
324 DPRINTF(PageTableWalker
,
325 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
328 entry
.writable
= entry
.writable
&& pte
.w
;
329 entry
.user
= entry
.user
&& pte
.u
;
330 if (badNX
|| !pte
.p
) {
332 fault
= pageFault(pte
.p
);
339 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* dataSize
;
345 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
346 entry
.uncacheable
= uncacheable
;
347 entry
.global
= pte
.g
;
348 entry
.patBit
= bits(pte
, 12);
349 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
355 DPRINTF(PageTableWalker
,
356 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
359 entry
.writable
= entry
.writable
&& pte
.w
;
360 entry
.user
= entry
.user
&& pte
.u
;
361 if (badNX
|| !pte
.p
) {
363 fault
= pageFault(pte
.p
);
366 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
367 entry
.uncacheable
= uncacheable
;
368 entry
.global
= pte
.g
;
369 entry
.patBit
= bits(pte
, 12);
370 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
375 DPRINTF(PageTableWalker
,
376 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
377 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* dataSize
;
380 fault
= pageFault(pte
.p
);
386 DPRINTF(PageTableWalker
,
387 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
390 entry
.writable
= pte
.w
;
392 if (badNX
|| !pte
.p
) {
394 fault
= pageFault(pte
.p
);
400 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* dataSize
;
406 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
407 entry
.uncacheable
= uncacheable
;
408 entry
.global
= pte
.g
;
409 entry
.patBit
= bits(pte
, 12);
410 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
416 DPRINTF(PageTableWalker
,
417 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
420 entry
.writable
= entry
.writable
&& pte
.w
;
421 entry
.user
= entry
.user
&& pte
.u
;
422 if (badNX
|| !pte
.p
) {
424 fault
= pageFault(pte
.p
);
427 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
428 entry
.uncacheable
= uncacheable
;
429 entry
.global
= pte
.g
;
430 entry
.patBit
= bits(pte
, 7);
431 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
436 DPRINTF(PageTableWalker
,
437 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
440 entry
.writable
= pte
.w
;
444 fault
= pageFault(pte
.p
);
451 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
457 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
458 entry
.uncacheable
= uncacheable
;
459 entry
.global
= pte
.g
;
460 entry
.patBit
= bits(pte
, 12);
461 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
467 DPRINTF(PageTableWalker
,
468 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
471 entry
.writable
= pte
.w
;
475 fault
= pageFault(pte
.p
);
480 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
484 DPRINTF(PageTableWalker
,
485 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
488 entry
.writable
= pte
.w
;
492 fault
= pageFault(pte
.p
);
495 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
496 entry
.uncacheable
= uncacheable
;
497 entry
.global
= pte
.g
;
498 entry
.patBit
= bits(pte
, 7);
499 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
504 panic("Unknown page table walker state %d!\n");
509 walker
->tlb
->insert(entry
.vaddr
, entry
);
512 PacketPtr oldRead
= read
;
513 //If we didn't return, we're setting up another read.
514 Request::Flags flags
= oldRead
->req
->getFlags();
515 flags
.set(Request::UNCACHEABLE
, uncacheable
);
517 new Request(nextRead
, oldRead
->getSize(), flags
, walker
->masterId
);
518 read
= new Packet(request
, MemCmd::ReadReq
);
520 // If we need to write, adjust the read packet to write the modified
521 // value back to memory.
524 write
->set
<uint64_t>(pte
);
525 write
->cmd
= MemCmd::WriteReq
;
537 Walker::WalkerState::endWalk()
546 Walker::WalkerState::setupWalk(Addr vaddr
)
549 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
550 // Check if we're in long mode or not
551 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
557 topAddr
= (cr3
.longPdtb
<< 12) + addr
.longl4
* dataSize
;
560 // We're in some flavor of legacy mode.
561 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
565 topAddr
= (cr3
.paePdtb
<< 5) + addr
.pael3
* dataSize
;
569 topAddr
= (cr3
.pdtb
<< 12) + addr
.norml2
* dataSize
;
574 // Do legacy non PSE.
584 Request::Flags flags
= Request::PHYSICAL
;
586 flags
.set(Request::UNCACHEABLE
);
587 RequestPtr request
= new Request(topAddr
, dataSize
, flags
,
589 read
= new Packet(request
, MemCmd::ReadReq
);
594 Walker::WalkerState::recvPacket(PacketPtr pkt
)
596 assert(pkt
->isResponse());
598 assert(state
== Waiting
);
601 // should not have a pending read it we also had one outstanding
604 // @todo someone should pay for this
605 pkt
->firstWordDelay
= pkt
->lastWordDelay
= 0;
609 PacketPtr write
= NULL
;
611 timingFault
= stepWalk(write
);
613 assert(timingFault
== NoFault
|| read
== NULL
);
615 writes
.push_back(write
);
621 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
624 if (timingFault
== NoFault
) {
626 * Finish the translation. Now that we now the right entry is
627 * in the TLB, this should work with no memory accesses.
628 * There could be new faults unrelated to the table walk like
629 * permissions violations, so we'll need the return value as
632 bool delayedResponse
;
633 Fault fault
= walker
->tlb
->translate(req
, tc
, NULL
, mode
,
634 delayedResponse
, true);
635 assert(!delayedResponse
);
636 // Let the CPU continue.
637 translation
->finish(fault
, req
, tc
, mode
);
639 // There was a fault during the walk. Let the CPU know.
640 translation
->finish(timingFault
, req
, tc
, mode
);
649 Walker::WalkerState::sendPackets()
651 //If we're already waiting for the port to become available, just return.
655 //Reads always have priority
657 PacketPtr pkt
= read
;
660 if (!walker
->sendTiming(this, pkt
)) {
667 //Send off as many of the writes as we can.
668 while (writes
.size()) {
669 PacketPtr write
= writes
.back();
672 if (!walker
->sendTiming(this, write
)) {
674 writes
.push_back(write
);
682 Walker::WalkerState::isRetrying()
688 Walker::WalkerState::isTiming()
694 Walker::WalkerState::wasStarted()
700 Walker::WalkerState::retry()
707 Walker::WalkerState::pageFault(bool present
)
709 DPRINTF(PageTableWalker
, "Raising page fault.\n");
710 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
711 if (mode
== BaseTLB::Execute
&& !enableNX
)
712 mode
= BaseTLB::Read
;
713 return std::make_shared
<PageFault
>(entry
.vaddr
, present
, mode
,
714 m5reg
.cpl
== 3, false);
717 /* end namespace X86ISA */ }
720 X86PagetableWalkerParams::create()
722 return new X86ISA::Walker(this);