2 * Copyright (c) 2007 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/x86/pagetable.hh"
41 #include "arch/x86/pagetable_walker.hh"
42 #include "arch/x86/tlb.hh"
43 #include "arch/x86/vtophys.hh"
44 #include "base/bitfield.hh"
45 #include "cpu/base.hh"
46 #include "cpu/thread_context.hh"
47 #include "debug/PageTableWalker.hh"
48 #include "mem/packet_access.hh"
49 #include "mem/request.hh"
50 #include "sim/system.hh"
54 // Unfortunately, the placement of the base field in a page table entry is
55 // very erratic and would make a mess here. It might be moved here at some
56 // point in the future.
57 BitUnion64(PageTableEntry
)
69 EndBitUnion(PageTableEntry
)
72 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
73 RequestPtr _req
, BaseTLB::Mode _mode
)
75 // TODO: in timing mode, instead of blocking when there are other
76 // outstanding requests, see if this request can be coalesced with
77 // another one (i.e. either coalesce or start walk)
78 WalkerState
* newState
= new WalkerState(this, _translation
, _req
);
79 newState
->initState(_tc
, _mode
, sys
->getMemoryMode() == Enums::timing
);
80 if (currStates
.size()) {
81 assert(newState
->isTiming());
82 DPRINTF(PageTableWalker
, "Walks in progress: %d\n", currStates
.size());
83 currStates
.push_back(newState
);
86 currStates
.push_back(newState
);
87 Fault fault
= newState
->startWalk();
88 if (!newState
->isTiming()) {
89 currStates
.pop_front();
97 Walker::startFunctional(ThreadContext
* _tc
, Addr
&addr
, Addr
&pageSize
,
100 funcState
.initState(_tc
, _mode
);
101 return funcState
.startFunctional(addr
, pageSize
);
105 Walker::WalkerPort::recvTiming(PacketPtr pkt
)
107 return walker
->recvTiming(pkt
);
111 Walker::recvTiming(PacketPtr pkt
)
113 if (pkt
->isResponse() || pkt
->wasNacked()) {
114 WalkerSenderState
* senderState
=
115 dynamic_cast<WalkerSenderState
*>(pkt
->senderState
);
116 pkt
->senderState
= senderState
->saved
;
117 WalkerState
* senderWalk
= senderState
->senderWalk
;
118 bool walkComplete
= senderWalk
->recvPacket(pkt
);
121 std::list
<WalkerState
*>::iterator iter
;
122 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
123 WalkerState
* walkerState
= *(iter
);
124 if (walkerState
== senderWalk
) {
125 iter
= currStates
.erase(iter
);
130 // Since we block requests when another is outstanding, we
131 // need to check if there is a waiting request to be serviced
132 if (currStates
.size()) {
133 WalkerState
* newState
= currStates
.front();
134 if (!newState
->wasStarted())
135 newState
->startWalk();
139 DPRINTF(PageTableWalker
, "Received strange packet\n");
145 Walker::WalkerPort::recvAtomic(PacketPtr pkt
)
151 Walker::WalkerPort::recvFunctional(PacketPtr pkt
)
157 Walker::WalkerPort::recvStatusChange(Status status
)
159 if (status
== RangeChange
) {
160 if (!snoopRangeSent
) {
161 snoopRangeSent
= true;
162 sendStatusChange(Port::RangeChange
);
167 panic("Unexpected recvStatusChange.\n");
171 Walker::WalkerPort::recvRetry()
179 std::list
<WalkerState
*>::iterator iter
;
180 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
181 WalkerState
* walkerState
= *(iter
);
182 if (walkerState
->isRetrying()) {
183 walkerState
->retry();
188 bool Walker::sendTiming(WalkerState
* sendingState
, PacketPtr pkt
)
190 pkt
->senderState
= new WalkerSenderState(sendingState
, pkt
->senderState
);
191 return port
.sendTiming(pkt
);
195 Walker::getPort(const std::string
&if_name
, int idx
)
197 if (if_name
== "port")
200 panic("No page table walker port named %s!\n", if_name
);
204 Walker::WalkerState::initState(ThreadContext
* _tc
,
205 BaseTLB::Mode _mode
, bool _isTiming
)
207 assert(state
== Ready
);
215 Walker::WalkerState::startWalk()
217 Fault fault
= NoFault
;
218 assert(started
== false);
220 setupWalk(req
->getVaddr());
224 timingFault
= NoFault
;
228 walker
->port
.sendAtomic(read
);
229 PacketPtr write
= NULL
;
230 fault
= stepWalk(write
);
231 assert(fault
== NoFault
|| read
== NULL
);
235 walker
->port
.sendAtomic(write
);
244 Walker::WalkerState::startFunctional(Addr
&addr
, Addr
&pageSize
)
246 Fault fault
= NoFault
;
247 assert(started
== false);
252 walker
->port
.sendFunctional(read
);
253 // On a functional access (page table lookup), writes should
254 // not happen so this pointer is ignored after stepWalk
255 PacketPtr write
= NULL
;
256 fault
= stepWalk(write
);
257 assert(fault
== NoFault
|| read
== NULL
);
261 pageSize
= entry
.size
;
268 Walker::WalkerState::stepWalk(PacketPtr
&write
)
270 assert(state
!= Ready
&& state
!= Waiting
);
271 Fault fault
= NoFault
;
275 pte
= read
->get
<uint64_t>();
277 pte
= read
->get
<uint32_t>();
278 VAddr vaddr
= entry
.vaddr
;
279 bool uncacheable
= pte
.pcd
;
281 bool doWrite
= false;
282 bool doTLBInsert
= false;
283 bool doEndWalk
= false;
284 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
287 DPRINTF(PageTableWalker
,
288 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
289 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* dataSize
;
292 entry
.writable
= pte
.w
;
294 if (badNX
|| !pte
.p
) {
296 fault
= pageFault(pte
.p
);
299 entry
.noExec
= pte
.nx
;
303 DPRINTF(PageTableWalker
,
304 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
305 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* dataSize
;
308 entry
.writable
= entry
.writable
&& pte
.w
;
309 entry
.user
= entry
.user
&& pte
.u
;
310 if (badNX
|| !pte
.p
) {
312 fault
= pageFault(pte
.p
);
318 DPRINTF(PageTableWalker
,
319 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
322 entry
.writable
= entry
.writable
&& pte
.w
;
323 entry
.user
= entry
.user
&& pte
.u
;
324 if (badNX
|| !pte
.p
) {
326 fault
= pageFault(pte
.p
);
331 entry
.size
= 4 * (1 << 10);
333 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* dataSize
;
338 entry
.size
= 2 * (1 << 20);
339 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
340 entry
.uncacheable
= uncacheable
;
341 entry
.global
= pte
.g
;
342 entry
.patBit
= bits(pte
, 12);
343 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
349 DPRINTF(PageTableWalker
,
350 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
353 entry
.writable
= entry
.writable
&& pte
.w
;
354 entry
.user
= entry
.user
&& pte
.u
;
355 if (badNX
|| !pte
.p
) {
357 fault
= pageFault(pte
.p
);
360 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
361 entry
.uncacheable
= uncacheable
;
362 entry
.global
= pte
.g
;
363 entry
.patBit
= bits(pte
, 12);
364 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
369 DPRINTF(PageTableWalker
,
370 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
371 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* dataSize
;
374 fault
= pageFault(pte
.p
);
380 DPRINTF(PageTableWalker
,
381 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
384 entry
.writable
= pte
.w
;
386 if (badNX
|| !pte
.p
) {
388 fault
= pageFault(pte
.p
);
393 entry
.size
= 4 * (1 << 10);
394 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* dataSize
;
399 entry
.size
= 2 * (1 << 20);
400 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
401 entry
.uncacheable
= uncacheable
;
402 entry
.global
= pte
.g
;
403 entry
.patBit
= bits(pte
, 12);
404 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
410 DPRINTF(PageTableWalker
,
411 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
414 entry
.writable
= entry
.writable
&& pte
.w
;
415 entry
.user
= entry
.user
&& pte
.u
;
416 if (badNX
|| !pte
.p
) {
418 fault
= pageFault(pte
.p
);
421 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
422 entry
.uncacheable
= uncacheable
;
423 entry
.global
= pte
.g
;
424 entry
.patBit
= bits(pte
, 7);
425 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
430 DPRINTF(PageTableWalker
,
431 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
434 entry
.writable
= pte
.w
;
438 fault
= pageFault(pte
.p
);
443 entry
.size
= 4 * (1 << 10);
445 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
450 entry
.size
= 4 * (1 << 20);
451 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
452 entry
.uncacheable
= uncacheable
;
453 entry
.global
= pte
.g
;
454 entry
.patBit
= bits(pte
, 12);
455 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
461 DPRINTF(PageTableWalker
,
462 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
465 entry
.writable
= pte
.w
;
469 fault
= pageFault(pte
.p
);
473 entry
.size
= 4 * (1 << 10);
474 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
478 DPRINTF(PageTableWalker
,
479 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
482 entry
.writable
= pte
.w
;
486 fault
= pageFault(pte
.p
);
489 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
490 entry
.uncacheable
= uncacheable
;
491 entry
.global
= pte
.g
;
492 entry
.patBit
= bits(pte
, 7);
493 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
498 panic("Unknown page table walker state %d!\n");
503 walker
->tlb
->insert(entry
.vaddr
, entry
);
506 PacketPtr oldRead
= read
;
507 //If we didn't return, we're setting up another read.
508 Request::Flags flags
= oldRead
->req
->getFlags();
509 flags
.set(Request::UNCACHEABLE
, uncacheable
);
511 new Request(nextRead
, oldRead
->getSize(), flags
);
512 read
= new Packet(request
, MemCmd::ReadReq
, Packet::Broadcast
);
514 // If we need to write, adjust the read packet to write the modified
515 // value back to memory.
518 write
->set
<uint64_t>(pte
);
519 write
->cmd
= MemCmd::WriteReq
;
520 write
->setDest(Packet::Broadcast
);
531 Walker::WalkerState::endWalk()
540 Walker::WalkerState::setupWalk(Addr vaddr
)
543 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
544 // Check if we're in long mode or not
545 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
551 topAddr
= (cr3
.longPdtb
<< 12) + addr
.longl4
* dataSize
;
554 // We're in some flavor of legacy mode.
555 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
559 topAddr
= (cr3
.paePdtb
<< 5) + addr
.pael3
* dataSize
;
563 topAddr
= (cr3
.pdtb
<< 12) + addr
.norml2
* dataSize
;
568 // Do legacy non PSE.
578 Request::Flags flags
= Request::PHYSICAL
;
580 flags
.set(Request::UNCACHEABLE
);
581 RequestPtr request
= new Request(topAddr
, dataSize
, flags
);
582 read
= new Packet(request
, MemCmd::ReadReq
, Packet::Broadcast
);
587 Walker::WalkerState::recvPacket(PacketPtr pkt
)
589 if (pkt
->isResponse() && !pkt
->wasNacked()) {
591 assert(state
== Waiting
);
597 PacketPtr write
= NULL
;
599 timingFault
= stepWalk(write
);
601 assert(timingFault
== NoFault
|| read
== NULL
);
603 writes
.push_back(write
);
609 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
612 if (timingFault
== NoFault
) {
614 * Finish the translation. Now that we now the right entry is
615 * in the TLB, this should work with no memory accesses.
616 * There could be new faults unrelated to the table walk like
617 * permissions violations, so we'll need the return value as
620 bool delayedResponse
;
621 Fault fault
= walker
->tlb
->translate(req
, tc
, NULL
, mode
,
622 delayedResponse
, true);
623 assert(!delayedResponse
);
624 // Let the CPU continue.
625 translation
->finish(fault
, req
, tc
, mode
);
627 // There was a fault during the walk. Let the CPU know.
628 translation
->finish(timingFault
, req
, tc
, mode
);
632 } else if (pkt
->wasNacked()) {
633 DPRINTF(PageTableWalker
, "Request was nacked. Entering retry state\n");
635 if (!walker
->sendTiming(this, pkt
)) {
638 if (pkt
->isWrite()) {
639 writes
.push_back(pkt
);
650 Walker::WalkerState::sendPackets()
652 //If we're already waiting for the port to become available, just return.
656 //Reads always have priority
658 PacketPtr pkt
= read
;
661 if (!walker
->sendTiming(this, pkt
)) {
668 //Send off as many of the writes as we can.
669 while (writes
.size()) {
670 PacketPtr write
= writes
.back();
673 if (!walker
->sendTiming(this, write
)) {
675 writes
.push_back(write
);
683 Walker::WalkerState::isRetrying()
689 Walker::WalkerState::isTiming()
695 Walker::WalkerState::wasStarted()
701 Walker::WalkerState::retry()
708 Walker::WalkerState::pageFault(bool present
)
710 DPRINTF(PageTableWalker
, "Raising page fault.\n");
711 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
712 if (mode
== BaseTLB::Execute
&& !enableNX
)
713 mode
= BaseTLB::Read
;
714 return new PageFault(entry
.vaddr
, present
, mode
, m5reg
.cpl
== 3, false);
717 /* end namespace X86ISA */ }
720 X86PagetableWalkerParams::create()
722 return new X86ISA::Walker(this);