2 * Copyright (c) 2007 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/x86/pagetable.hh"
41 #include "arch/x86/pagetable_walker.hh"
42 #include "arch/x86/tlb.hh"
43 #include "arch/x86/vtophys.hh"
44 #include "base/bitfield.hh"
45 #include "cpu/base.hh"
46 #include "cpu/thread_context.hh"
47 #include "debug/PageTableWalker.hh"
48 #include "mem/packet_access.hh"
49 #include "mem/request.hh"
50 #include "sim/system.hh"
54 // Unfortunately, the placement of the base field in a page table entry is
55 // very erratic and would make a mess here. It might be moved here at some
56 // point in the future.
57 BitUnion64(PageTableEntry
)
69 EndBitUnion(PageTableEntry
)
72 Walker::start(ThreadContext
* _tc
, BaseTLB::Translation
*_translation
,
73 RequestPtr _req
, BaseTLB::Mode _mode
)
75 // TODO: in timing mode, instead of blocking when there are other
76 // outstanding requests, see if this request can be coalesced with
77 // another one (i.e. either coalesce or start walk)
78 WalkerState
* newState
= new WalkerState(this, _translation
, _req
);
79 newState
->initState(_tc
, _mode
, sys
->getMemoryMode() == Enums::timing
);
80 if (currStates
.size()) {
81 assert(newState
->isTiming());
82 DPRINTF(PageTableWalker
, "Walks in progress: %d\n", currStates
.size());
83 currStates
.push_back(newState
);
86 currStates
.push_back(newState
);
87 Fault fault
= newState
->startWalk();
88 if (!newState
->isTiming()) {
89 currStates
.pop_front();
97 Walker::startFunctional(ThreadContext
* _tc
, Addr
&addr
, Addr
&pageSize
,
100 funcState
.initState(_tc
, _mode
);
101 return funcState
.startFunctional(addr
, pageSize
);
105 Walker::WalkerPort::recvTiming(PacketPtr pkt
)
107 return walker
->recvTiming(pkt
);
111 Walker::recvTiming(PacketPtr pkt
)
113 if (pkt
->isResponse() || pkt
->wasNacked()) {
114 WalkerSenderState
* senderState
=
115 dynamic_cast<WalkerSenderState
*>(pkt
->senderState
);
116 pkt
->senderState
= senderState
->saved
;
117 WalkerState
* senderWalk
= senderState
->senderWalk
;
118 bool walkComplete
= senderWalk
->recvPacket(pkt
);
121 std::list
<WalkerState
*>::iterator iter
;
122 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
123 WalkerState
* walkerState
= *(iter
);
124 if (walkerState
== senderWalk
) {
125 iter
= currStates
.erase(iter
);
130 // Since we block requests when another is outstanding, we
131 // need to check if there is a waiting request to be serviced
132 if (currStates
.size()) {
133 WalkerState
* newState
= currStates
.front();
134 if (!newState
->wasStarted())
135 newState
->startWalk();
139 DPRINTF(PageTableWalker
, "Received strange packet\n");
145 Walker::WalkerPort::recvAtomic(PacketPtr pkt
)
151 Walker::WalkerPort::recvFunctional(PacketPtr pkt
)
157 Walker::WalkerPort::recvRetry()
165 std::list
<WalkerState
*>::iterator iter
;
166 for (iter
= currStates
.begin(); iter
!= currStates
.end(); iter
++) {
167 WalkerState
* walkerState
= *(iter
);
168 if (walkerState
->isRetrying()) {
169 walkerState
->retry();
174 bool Walker::sendTiming(WalkerState
* sendingState
, PacketPtr pkt
)
176 pkt
->senderState
= new WalkerSenderState(sendingState
, pkt
->senderState
);
177 return port
.sendTiming(pkt
);
181 Walker::getMasterPort(const std::string
&if_name
, int idx
)
183 if (if_name
== "port")
186 return MemObject::getMasterPort(if_name
, idx
);
190 Walker::WalkerState::initState(ThreadContext
* _tc
,
191 BaseTLB::Mode _mode
, bool _isTiming
)
193 assert(state
== Ready
);
201 Walker::WalkerState::startWalk()
203 Fault fault
= NoFault
;
204 assert(started
== false);
206 setupWalk(req
->getVaddr());
210 timingFault
= NoFault
;
214 walker
->port
.sendAtomic(read
);
215 PacketPtr write
= NULL
;
216 fault
= stepWalk(write
);
217 assert(fault
== NoFault
|| read
== NULL
);
221 walker
->port
.sendAtomic(write
);
230 Walker::WalkerState::startFunctional(Addr
&addr
, Addr
&pageSize
)
232 Fault fault
= NoFault
;
233 assert(started
== false);
238 walker
->port
.sendFunctional(read
);
239 // On a functional access (page table lookup), writes should
240 // not happen so this pointer is ignored after stepWalk
241 PacketPtr write
= NULL
;
242 fault
= stepWalk(write
);
243 assert(fault
== NoFault
|| read
== NULL
);
247 pageSize
= entry
.size
;
254 Walker::WalkerState::stepWalk(PacketPtr
&write
)
256 assert(state
!= Ready
&& state
!= Waiting
);
257 Fault fault
= NoFault
;
261 pte
= read
->get
<uint64_t>();
263 pte
= read
->get
<uint32_t>();
264 VAddr vaddr
= entry
.vaddr
;
265 bool uncacheable
= pte
.pcd
;
267 bool doWrite
= false;
268 bool doTLBInsert
= false;
269 bool doEndWalk
= false;
270 bool badNX
= pte
.nx
&& mode
== BaseTLB::Execute
&& enableNX
;
273 DPRINTF(PageTableWalker
,
274 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte
);
275 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl3
* dataSize
;
278 entry
.writable
= pte
.w
;
280 if (badNX
|| !pte
.p
) {
282 fault
= pageFault(pte
.p
);
285 entry
.noExec
= pte
.nx
;
289 DPRINTF(PageTableWalker
,
290 "Got long mode PDP entry %#016x.\n", (uint64_t)pte
);
291 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl2
* dataSize
;
294 entry
.writable
= entry
.writable
&& pte
.w
;
295 entry
.user
= entry
.user
&& pte
.u
;
296 if (badNX
|| !pte
.p
) {
298 fault
= pageFault(pte
.p
);
304 DPRINTF(PageTableWalker
,
305 "Got long mode PD entry %#016x.\n", (uint64_t)pte
);
308 entry
.writable
= entry
.writable
&& pte
.w
;
309 entry
.user
= entry
.user
&& pte
.u
;
310 if (badNX
|| !pte
.p
) {
312 fault
= pageFault(pte
.p
);
317 entry
.size
= 4 * (1 << 10);
319 ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.longl1
* dataSize
;
324 entry
.size
= 2 * (1 << 20);
325 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
326 entry
.uncacheable
= uncacheable
;
327 entry
.global
= pte
.g
;
328 entry
.patBit
= bits(pte
, 12);
329 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
335 DPRINTF(PageTableWalker
,
336 "Got long mode PTE entry %#016x.\n", (uint64_t)pte
);
339 entry
.writable
= entry
.writable
&& pte
.w
;
340 entry
.user
= entry
.user
&& pte
.u
;
341 if (badNX
|| !pte
.p
) {
343 fault
= pageFault(pte
.p
);
346 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
347 entry
.uncacheable
= uncacheable
;
348 entry
.global
= pte
.g
;
349 entry
.patBit
= bits(pte
, 12);
350 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
355 DPRINTF(PageTableWalker
,
356 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte
);
357 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael2
* dataSize
;
360 fault
= pageFault(pte
.p
);
366 DPRINTF(PageTableWalker
,
367 "Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte
);
370 entry
.writable
= pte
.w
;
372 if (badNX
|| !pte
.p
) {
374 fault
= pageFault(pte
.p
);
379 entry
.size
= 4 * (1 << 10);
380 nextRead
= ((uint64_t)pte
& (mask(40) << 12)) + vaddr
.pael1
* dataSize
;
385 entry
.size
= 2 * (1 << 20);
386 entry
.paddr
= (uint64_t)pte
& (mask(31) << 21);
387 entry
.uncacheable
= uncacheable
;
388 entry
.global
= pte
.g
;
389 entry
.patBit
= bits(pte
, 12);
390 entry
.vaddr
= entry
.vaddr
& ~((2 * (1 << 20)) - 1);
396 DPRINTF(PageTableWalker
,
397 "Got legacy mode PAE PTE entry %#08x.\n", (uint32_t)pte
);
400 entry
.writable
= entry
.writable
&& pte
.w
;
401 entry
.user
= entry
.user
&& pte
.u
;
402 if (badNX
|| !pte
.p
) {
404 fault
= pageFault(pte
.p
);
407 entry
.paddr
= (uint64_t)pte
& (mask(40) << 12);
408 entry
.uncacheable
= uncacheable
;
409 entry
.global
= pte
.g
;
410 entry
.patBit
= bits(pte
, 7);
411 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
416 DPRINTF(PageTableWalker
,
417 "Got legacy mode PSE PD entry %#08x.\n", (uint32_t)pte
);
420 entry
.writable
= pte
.w
;
424 fault
= pageFault(pte
.p
);
429 entry
.size
= 4 * (1 << 10);
431 ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
436 entry
.size
= 4 * (1 << 20);
437 entry
.paddr
= bits(pte
, 20, 13) << 32 | bits(pte
, 31, 22) << 22;
438 entry
.uncacheable
= uncacheable
;
439 entry
.global
= pte
.g
;
440 entry
.patBit
= bits(pte
, 12);
441 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 20)) - 1);
447 DPRINTF(PageTableWalker
,
448 "Got legacy mode PD entry %#08x.\n", (uint32_t)pte
);
451 entry
.writable
= pte
.w
;
455 fault
= pageFault(pte
.p
);
459 entry
.size
= 4 * (1 << 10);
460 nextRead
= ((uint64_t)pte
& (mask(20) << 12)) + vaddr
.norml2
* dataSize
;
464 DPRINTF(PageTableWalker
,
465 "Got legacy mode PTE entry %#08x.\n", (uint32_t)pte
);
468 entry
.writable
= pte
.w
;
472 fault
= pageFault(pte
.p
);
475 entry
.paddr
= (uint64_t)pte
& (mask(20) << 12);
476 entry
.uncacheable
= uncacheable
;
477 entry
.global
= pte
.g
;
478 entry
.patBit
= bits(pte
, 7);
479 entry
.vaddr
= entry
.vaddr
& ~((4 * (1 << 10)) - 1);
484 panic("Unknown page table walker state %d!\n");
489 walker
->tlb
->insert(entry
.vaddr
, entry
);
492 PacketPtr oldRead
= read
;
493 //If we didn't return, we're setting up another read.
494 Request::Flags flags
= oldRead
->req
->getFlags();
495 flags
.set(Request::UNCACHEABLE
, uncacheable
);
497 new Request(nextRead
, oldRead
->getSize(), flags
, walker
->masterId
);
498 read
= new Packet(request
, MemCmd::ReadReq
, Packet::Broadcast
);
500 // If we need to write, adjust the read packet to write the modified
501 // value back to memory.
504 write
->set
<uint64_t>(pte
);
505 write
->cmd
= MemCmd::WriteReq
;
506 write
->setDest(Packet::Broadcast
);
517 Walker::WalkerState::endWalk()
526 Walker::WalkerState::setupWalk(Addr vaddr
)
529 CR3 cr3
= tc
->readMiscRegNoEffect(MISCREG_CR3
);
530 // Check if we're in long mode or not
531 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
537 topAddr
= (cr3
.longPdtb
<< 12) + addr
.longl4
* dataSize
;
540 // We're in some flavor of legacy mode.
541 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
545 topAddr
= (cr3
.paePdtb
<< 5) + addr
.pael3
* dataSize
;
549 topAddr
= (cr3
.pdtb
<< 12) + addr
.norml2
* dataSize
;
554 // Do legacy non PSE.
564 Request::Flags flags
= Request::PHYSICAL
;
566 flags
.set(Request::UNCACHEABLE
);
567 RequestPtr request
= new Request(topAddr
, dataSize
, flags
, walker
->masterId
);
568 read
= new Packet(request
, MemCmd::ReadReq
, Packet::Broadcast
);
573 Walker::WalkerState::recvPacket(PacketPtr pkt
)
575 if (pkt
->isResponse() && !pkt
->wasNacked()) {
577 assert(state
== Waiting
);
583 PacketPtr write
= NULL
;
585 timingFault
= stepWalk(write
);
587 assert(timingFault
== NoFault
|| read
== NULL
);
589 writes
.push_back(write
);
595 if (inflight
== 0 && read
== NULL
&& writes
.size() == 0) {
598 if (timingFault
== NoFault
) {
600 * Finish the translation. Now that we now the right entry is
601 * in the TLB, this should work with no memory accesses.
602 * There could be new faults unrelated to the table walk like
603 * permissions violations, so we'll need the return value as
606 bool delayedResponse
;
607 Fault fault
= walker
->tlb
->translate(req
, tc
, NULL
, mode
,
608 delayedResponse
, true);
609 assert(!delayedResponse
);
610 // Let the CPU continue.
611 translation
->finish(fault
, req
, tc
, mode
);
613 // There was a fault during the walk. Let the CPU know.
614 translation
->finish(timingFault
, req
, tc
, mode
);
618 } else if (pkt
->wasNacked()) {
619 DPRINTF(PageTableWalker
, "Request was nacked. Entering retry state\n");
621 if (!walker
->sendTiming(this, pkt
)) {
624 if (pkt
->isWrite()) {
625 writes
.push_back(pkt
);
636 Walker::WalkerState::sendPackets()
638 //If we're already waiting for the port to become available, just return.
642 //Reads always have priority
644 PacketPtr pkt
= read
;
647 if (!walker
->sendTiming(this, pkt
)) {
654 //Send off as many of the writes as we can.
655 while (writes
.size()) {
656 PacketPtr write
= writes
.back();
659 if (!walker
->sendTiming(this, write
)) {
661 writes
.push_back(write
);
669 Walker::WalkerState::isRetrying()
675 Walker::WalkerState::isTiming()
681 Walker::WalkerState::wasStarted()
687 Walker::WalkerState::retry()
694 Walker::WalkerState::pageFault(bool present
)
696 DPRINTF(PageTableWalker
, "Raising page fault.\n");
697 HandyM5Reg m5reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
698 if (mode
== BaseTLB::Execute
&& !enableNX
)
699 mode
= BaseTLB::Read
;
700 return new PageFault(entry
.vaddr
, present
, mode
, m5reg
.cpl
== 3, false);
703 /* end namespace X86ISA */ }
706 X86PagetableWalkerParams::create()
708 return new X86ISA::Walker(this);