2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include "arch/x86/process.hh"
47 #include "arch/x86/fs_workload.hh"
48 #include "arch/x86/isa_traits.hh"
49 #include "arch/x86/regs/misc.hh"
50 #include "arch/x86/regs/segment.hh"
51 #include "arch/x86/types.hh"
52 #include "base/loader/elf_object.hh"
53 #include "base/loader/object_file.hh"
54 #include "base/logging.hh"
55 #include "base/trace.hh"
56 #include "cpu/thread_context.hh"
57 #include "debug/Stack.hh"
58 #include "mem/multi_level_page_table.hh"
59 #include "mem/page_table.hh"
60 #include "params/Process.hh"
61 #include "sim/aux_vector.hh"
62 #include "sim/process_impl.hh"
63 #include "sim/syscall_desc.hh"
64 #include "sim/syscall_return.hh"
65 #include "sim/system.hh"
68 using namespace X86ISA
;
70 template class MultiLevelPageTable
<LongModePTE
<47, 39>,
73 LongModePTE
<20, 12> >;
74 typedef MultiLevelPageTable
<LongModePTE
<47, 39>,
77 LongModePTE
<20, 12> > ArchPageTable
;
79 X86Process::X86Process(const ProcessParams
¶ms
,
80 ::Loader::ObjectFile
*objFile
) :
81 Process(params
, params
.useArchPT
?
82 static_cast<EmulationPageTable
*>(
83 new ArchPageTable(params
.name
, params
.pid
,
84 params
.system
, PageBytes
)) :
85 new EmulationPageTable(params
.name
, params
.pid
,
91 void X86Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
92 Process
*p
, RegVal flags
)
94 Process::clone(old_tc
, new_tc
, p
, flags
);
95 X86Process
*process
= (X86Process
*)p
;
99 X86_64Process::X86_64Process(const ProcessParams
¶ms
,
100 ::Loader::ObjectFile
*objFile
) :
101 X86Process(params
, objFile
)
103 vsyscallPage
.base
= 0xffffffffff600000ULL
;
104 vsyscallPage
.size
= PageBytes
;
105 vsyscallPage
.vtimeOffset
= 0x400;
106 vsyscallPage
.vgettimeofdayOffset
= 0x0;
108 Addr brk_point
= roundUp(image
.maxAddr(), PageBytes
);
109 Addr stack_base
= 0x7FFFFFFFF000ULL
;
110 Addr max_stack_size
= 8 * 1024 * 1024;
111 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
112 Addr mmap_end
= 0x7FFFF7FFF000ULL
;
114 memState
= make_shared
<MemState
>(this, brk_point
, stack_base
,
115 max_stack_size
, next_thread_stack_base
,
120 I386Process::I386Process(const ProcessParams
¶ms
,
121 ::Loader::ObjectFile
*objFile
) :
122 X86Process(params
, objFile
)
125 panic("KVM CPU model does not support 32 bit processes");
127 _gdtStart
= ULL(0xffffd000);
128 _gdtSize
= PageBytes
;
130 vsyscallPage
.base
= 0xffffe000ULL
;
131 vsyscallPage
.size
= PageBytes
;
132 vsyscallPage
.vsyscallOffset
= 0x400;
133 vsyscallPage
.vsysexitOffset
= 0x410;
135 Addr brk_point
= roundUp(image
.maxAddr(), PageBytes
);
136 Addr stack_base
= _gdtStart
;
137 Addr max_stack_size
= 8 * 1024 * 1024;
138 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
139 Addr mmap_end
= 0xB7FFF000ULL
;
141 memState
= make_shared
<MemState
>(this, brk_point
, stack_base
,
142 max_stack_size
, next_thread_stack_base
,
147 X86_64Process::initState()
149 X86Process::initState();
156 // Set up the vsyscall page for this process.
157 memState
->mapRegion(vsyscallPage
.base
, vsyscallPage
.size
, "vsyscall");
158 uint8_t vtimeBlob
[] = {
159 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
160 0x0f,0x05, // syscall
163 initVirtMem
->writeBlob(vsyscallPage
.base
+ vsyscallPage
.vtimeOffset
,
164 vtimeBlob
, sizeof(vtimeBlob
));
166 uint8_t vgettimeofdayBlob
[] = {
167 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
168 0x0f,0x05, // syscall
171 initVirtMem
->writeBlob(
172 vsyscallPage
.base
+ vsyscallPage
.vgettimeofdayOffset
,
173 vgettimeofdayBlob
, sizeof(vgettimeofdayBlob
));
176 PortProxy physProxy
= system
->physProxy
;
178 Addr syscallCodePhysAddr
= system
->allocPhysPages(1);
179 Addr gdtPhysAddr
= system
->allocPhysPages(1);
180 Addr idtPhysAddr
= system
->allocPhysPages(1);
181 Addr istPhysAddr
= system
->allocPhysPages(1);
182 Addr tssPhysAddr
= system
->allocPhysPages(1);
183 Addr pfHandlerPhysAddr
= system
->allocPhysPages(1);
188 uint8_t numGDTEntries
= 0;
189 uint64_t nullDescriptor
= 0;
190 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
194 SegDescriptor initDesc
= 0;
195 initDesc
.type
.codeOrData
= 0; // code or data type
196 initDesc
.type
.c
= 0; // conforming
197 initDesc
.type
.r
= 1; // readable
198 initDesc
.dpl
= 0; // privilege
199 initDesc
.p
= 1; // present
200 initDesc
.l
= 1; // longmode - 64 bit
201 initDesc
.d
= 0; // operand size
203 initDesc
.s
= 1; // system segment
204 initDesc
.limit
= 0xFFFFFFFF;
207 //64 bit code segment
208 SegDescriptor csLowPLDesc
= initDesc
;
209 csLowPLDesc
.type
.codeOrData
= 1;
211 uint64_t csLowPLDescVal
= csLowPLDesc
;
212 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
217 SegSelector csLowPL
= 0;
218 csLowPL
.si
= numGDTEntries
- 1;
221 //64 bit data segment
222 SegDescriptor dsLowPLDesc
= initDesc
;
223 dsLowPLDesc
.type
.codeOrData
= 0;
225 uint64_t dsLowPLDescVal
= dsLowPLDesc
;
226 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
231 SegSelector dsLowPL
= 0;
232 dsLowPL
.si
= numGDTEntries
- 1;
235 //64 bit data segment
236 SegDescriptor dsDesc
= initDesc
;
237 dsDesc
.type
.codeOrData
= 0;
239 uint64_t dsDescVal
= dsDesc
;
240 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
246 ds
.si
= numGDTEntries
- 1;
249 //64 bit code segment
250 SegDescriptor csDesc
= initDesc
;
251 csDesc
.type
.codeOrData
= 1;
253 uint64_t csDescVal
= csDesc
;
254 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
260 cs
.si
= numGDTEntries
- 1;
263 SegSelector scall
= 0;
264 scall
.si
= csLowPL
.si
;
267 SegSelector sret
= 0;
268 sret
.si
= dsLowPL
.si
;
271 /* In long mode the TSS has been extended to 16 Bytes */
272 TSSlow TSSDescLow
= 0;
273 TSSDescLow
.type
= 0xB;
274 TSSDescLow
.dpl
= 0; // Privelege level 0
275 TSSDescLow
.p
= 1; // Present
276 TSSDescLow
.limit
= 0xFFFFFFFF;
277 TSSDescLow
.base
= bits(TSSVirtAddr
, 31, 0);
279 TSShigh TSSDescHigh
= 0;
280 TSSDescHigh
.base
= bits(TSSVirtAddr
, 63, 32);
285 } tssDescVal
= {TSSDescLow
, TSSDescHigh
};
287 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
288 &tssDescVal
, sizeof(tssDescVal
));
292 SegSelector tssSel
= 0;
293 tssSel
.si
= numGDTEntries
- 1;
295 uint64_t tss_base_addr
= (TSSDescHigh
.base
<< 32) | TSSDescLow
.base
;
296 uint64_t tss_limit
= TSSDescLow
.limit
;
298 SegAttr tss_attr
= 0;
300 tss_attr
.type
= TSSDescLow
.type
;
301 tss_attr
.dpl
= TSSDescLow
.dpl
;
302 tss_attr
.present
= TSSDescLow
.p
;
303 tss_attr
.granularity
= TSSDescLow
.g
;
304 tss_attr
.unusable
= 0;
306 for (int i
= 0; i
< contextIds
.size(); i
++) {
307 ThreadContext
*tc
= system
->threads
[contextIds
[i
]];
309 tc
->setMiscReg(MISCREG_CS
, cs
);
310 tc
->setMiscReg(MISCREG_DS
, ds
);
311 tc
->setMiscReg(MISCREG_ES
, ds
);
312 tc
->setMiscReg(MISCREG_FS
, ds
);
313 tc
->setMiscReg(MISCREG_GS
, ds
);
314 tc
->setMiscReg(MISCREG_SS
, ds
);
317 tc
->setMiscReg(MISCREG_TSL
, 0);
321 tc
->setMiscReg(MISCREG_TSL_ATTR
, tslAttr
);
323 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
324 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 8 * numGDTEntries
- 1);
326 tc
->setMiscReg(MISCREG_TR
, tssSel
);
327 tc
->setMiscReg(MISCREG_TR_BASE
, tss_base_addr
);
328 tc
->setMiscReg(MISCREG_TR_EFF_BASE
, 0);
329 tc
->setMiscReg(MISCREG_TR_LIMIT
, tss_limit
);
330 tc
->setMiscReg(MISCREG_TR_ATTR
, tss_attr
);
332 //Start using longmode segments.
333 installSegDesc(tc
, SEGMENT_REG_CS
, csDesc
, true);
334 installSegDesc(tc
, SEGMENT_REG_DS
, dsDesc
, true);
335 installSegDesc(tc
, SEGMENT_REG_ES
, dsDesc
, true);
336 installSegDesc(tc
, SEGMENT_REG_FS
, dsDesc
, true);
337 installSegDesc(tc
, SEGMENT_REG_GS
, dsDesc
, true);
338 installSegDesc(tc
, SEGMENT_REG_SS
, dsDesc
, true);
341 efer
.sce
= 1; // Enable system call extensions.
342 efer
.lme
= 1; // Enable long mode.
343 efer
.lma
= 1; // Activate long mode.
344 efer
.nxe
= 1; // Enable nx support.
345 efer
.svme
= 0; // Enable svm support for now.
346 efer
.ffxsr
= 0; // Turn on fast fxsave and fxrstor.
347 tc
->setMiscReg(MISCREG_EFER
, efer
);
349 //Set up the registers that describe the operating mode.
351 cr0
.pg
= 1; // Turn on paging.
352 cr0
.cd
= 0; // Don't disable caching.
353 cr0
.nw
= 0; // This is bit is defined to be ignored.
354 cr0
.am
= 1; // No alignment checking
355 cr0
.wp
= 1; // Supervisor mode can write read only pages
357 cr0
.et
= 1; // This should always be 1
358 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
359 // would be pointless.
360 cr0
.em
= 0; // Allow x87 instructions to execute natively.
361 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
362 // setting it to one.
363 cr0
.pe
= 1; // We're definitely in protected mode.
364 tc
->setMiscReg(MISCREG_CR0
, cr0
);
367 tc
->setMiscReg(MISCREG_CR2
, cr2
);
369 CR3 cr3
= dynamic_cast<ArchPageTable
*>(pTable
)->basePtr();
370 tc
->setMiscReg(MISCREG_CR3
, cr3
);
374 cr4
.osxsave
= 0; // Enable XSAVE and Proc Extended States
375 cr4
.osxmmexcpt
= 0; // Operating System Unmasked Exception
376 cr4
.osfxsr
= 1; // Operating System FXSave/FSRSTOR Support
377 cr4
.pce
= 0; // Performance-Monitoring Counter Enable
378 cr4
.pge
= 0; // Page-Global Enable
379 cr4
.mce
= 0; // Machine Check Enable
380 cr4
.pae
= 1; // Physical-Address Extension
381 cr4
.pse
= 0; // Page Size Extensions
382 cr4
.de
= 0; // Debugging Extensions
383 cr4
.tsd
= 0; // Time Stamp Disable
384 cr4
.pvi
= 0; // Protected-Mode Virtual Interrupts
385 cr4
.vme
= 0; // Virtual-8086 Mode Extensions
387 tc
->setMiscReg(MISCREG_CR4
, cr4
);
390 tc
->setMiscReg(MISCREG_CR8
, cr8
);
392 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
394 tc
->setMiscReg(MISCREG_APIC_BASE
, 0xfee00900);
396 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
397 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 0xffff);
399 tc
->setMiscReg(MISCREG_IDTR_BASE
, IDTVirtAddr
);
400 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
402 /* enabling syscall and sysret */
403 RegVal star
= ((RegVal
)sret
<< 48) | ((RegVal
)scall
<< 32);
404 tc
->setMiscReg(MISCREG_STAR
, star
);
405 RegVal lstar
= (RegVal
)syscallCodeVirtAddr
;
406 tc
->setMiscReg(MISCREG_LSTAR
, lstar
);
407 RegVal sfmask
= (1 << 8) | (1 << 10); // TF | DF
408 tc
->setMiscReg(MISCREG_SF_MASK
, sfmask
);
411 /* Set up the content of the TSS and write it to physical memory. */
414 uint32_t reserved0
; // +00h
415 uint32_t RSP0_low
; // +04h
416 uint32_t RSP0_high
; // +08h
417 uint32_t RSP1_low
; // +0Ch
418 uint32_t RSP1_high
; // +10h
419 uint32_t RSP2_low
; // +14h
420 uint32_t RSP2_high
; // +18h
421 uint32_t reserved1
; // +1Ch
422 uint32_t reserved2
; // +20h
423 uint32_t IST1_low
; // +24h
424 uint32_t IST1_high
; // +28h
425 uint32_t IST2_low
; // +2Ch
426 uint32_t IST2_high
; // +30h
427 uint32_t IST3_low
; // +34h
428 uint32_t IST3_high
; // +38h
429 uint32_t IST4_low
; // +3Ch
430 uint32_t IST4_high
; // +40h
431 uint32_t IST5_low
; // +44h
432 uint32_t IST5_high
; // +48h
433 uint32_t IST6_low
; // +4Ch
434 uint32_t IST6_high
; // +50h
435 uint32_t IST7_low
; // +54h
436 uint32_t IST7_high
; // +58h
437 uint32_t reserved3
; // +5Ch
438 uint32_t reserved4
; // +60h
439 uint16_t reserved5
; // +64h
440 uint16_t IO_MapBase
; // +66h
443 /** setting Interrupt Stack Table */
444 uint64_t IST_start
= ISTVirtAddr
+ PageBytes
;
445 tss
.IST1_low
= IST_start
;
446 tss
.IST1_high
= IST_start
>> 32;
447 tss
.RSP0_low
= tss
.IST1_low
;
448 tss
.RSP0_high
= tss
.IST1_high
;
449 tss
.RSP1_low
= tss
.IST1_low
;
450 tss
.RSP1_high
= tss
.IST1_high
;
451 tss
.RSP2_low
= tss
.IST1_low
;
452 tss
.RSP2_high
= tss
.IST1_high
;
453 physProxy
.writeBlob(tssPhysAddr
, &tss
, sizeof(tss
));
455 /* Setting IDT gates */
456 GateDescriptorLow PFGateLow
= 0;
457 PFGateLow
.offsetHigh
= bits(PFHandlerVirtAddr
, 31, 16);
458 PFGateLow
.offsetLow
= bits(PFHandlerVirtAddr
, 15, 0);
459 PFGateLow
.selector
= csLowPL
;
462 PFGateLow
.type
= 0xe; // gate interrupt type
463 PFGateLow
.IST
= 0; // setting IST to 0 and using RSP0
465 GateDescriptorHigh PFGateHigh
= 0;
466 PFGateHigh
.offset
= bits(PFHandlerVirtAddr
, 63, 32);
471 } PFGate
= {PFGateLow
, PFGateHigh
};
473 physProxy
.writeBlob(idtPhysAddr
+ 0xE0, &PFGate
, sizeof(PFGate
));
475 /* System call handler */
476 uint8_t syscallBlob
[] = {
477 // mov %rax, (0xffffc90000005600)
478 0x48, 0xa3, 0x00, 0x60, 0x00,
479 0x00, 0x00, 0xc9, 0xff, 0xff,
484 physProxy
.writeBlob(syscallCodePhysAddr
,
485 syscallBlob
, sizeof(syscallBlob
));
487 /** Page fault handler */
488 uint8_t faultBlob
[] = {
489 // mov %rax, (0xffffc90000005700)
490 0x48, 0xa3, 0x00, 0x61, 0x00,
491 0x00, 0x00, 0xc9, 0xff, 0xff,
492 // add $0x8, %rsp # skip error
493 0x48, 0x83, 0xc4, 0x08,
498 physProxy
.writeBlob(pfHandlerPhysAddr
, faultBlob
, sizeof(faultBlob
));
500 /* Syscall handler */
501 pTable
->map(syscallCodeVirtAddr
, syscallCodePhysAddr
,
504 pTable
->map(GDTVirtAddr
, gdtPhysAddr
, PageBytes
, false);
506 pTable
->map(IDTVirtAddr
, idtPhysAddr
, PageBytes
, false);
508 pTable
->map(TSSVirtAddr
, tssPhysAddr
, PageBytes
, false);
510 pTable
->map(ISTVirtAddr
, istPhysAddr
, PageBytes
, false);
512 pTable
->map(PFHandlerVirtAddr
, pfHandlerPhysAddr
, PageBytes
, false);
513 /* MMIO region for m5ops */
514 pTable
->map(MMIORegionVirtAddr
, MMIORegionPhysAddr
,
515 16 * PageBytes
, false);
517 for (int i
= 0; i
< contextIds
.size(); i
++) {
518 ThreadContext
* tc
= system
->threads
[contextIds
[i
]];
520 SegAttr dataAttr
= 0;
522 dataAttr
.unusable
= 0;
523 dataAttr
.defaultSize
= 1;
524 dataAttr
.longMode
= 1;
526 dataAttr
.granularity
= 1;
527 dataAttr
.present
= 1;
529 dataAttr
.writable
= 1;
530 dataAttr
.readable
= 1;
531 dataAttr
.expandDown
= 0;
534 // Initialize the segment registers.
535 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
536 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
537 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
538 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
544 csAttr
.defaultSize
= 0;
547 csAttr
.granularity
= 1;
552 csAttr
.expandDown
= 0;
555 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
558 efer
.sce
= 1; // Enable system call extensions.
559 efer
.lme
= 1; // Enable long mode.
560 efer
.lma
= 1; // Activate long mode.
561 efer
.nxe
= 1; // Enable nx support.
562 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
563 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
564 tc
->setMiscReg(MISCREG_EFER
, efer
);
566 // Set up the registers that describe the operating mode.
568 cr0
.pg
= 1; // Turn on paging.
569 cr0
.cd
= 0; // Don't disable caching.
570 cr0
.nw
= 0; // This is bit is defined to be ignored.
571 cr0
.am
= 0; // No alignment checking
572 cr0
.wp
= 0; // Supervisor mode can write read only pages
574 cr0
.et
= 1; // This should always be 1
575 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
576 // would be pointless.
577 cr0
.em
= 0; // Allow x87 instructions to execute natively.
578 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
579 // setting it to one.
580 cr0
.pe
= 1; // We're definitely in protected mode.
581 tc
->setMiscReg(MISCREG_CR0
, cr0
);
583 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
589 I386Process::initState()
591 X86Process::initState();
596 * Set up a GDT for this process. The whole GDT wouldn't really be for
597 * this process, but the only parts we care about are.
599 allocateMem(_gdtStart
, _gdtSize
);
601 assert(_gdtSize
% sizeof(zero
) == 0);
602 for (Addr gdtCurrent
= _gdtStart
;
603 gdtCurrent
< _gdtStart
+ _gdtSize
; gdtCurrent
+= sizeof(zero
)) {
604 initVirtMem
->write(gdtCurrent
, zero
);
607 // Set up the vsyscall page for this process.
608 memState
->mapRegion(vsyscallPage
.base
, vsyscallPage
.size
, "vsyscall");
609 uint8_t vsyscallBlob
[] = {
613 0x89, 0xe5, // mov %esp, %ebp
614 0x0f, 0x34 // sysenter
616 initVirtMem
->writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
,
617 vsyscallBlob
, sizeof(vsyscallBlob
));
619 uint8_t vsysexitBlob
[] = {
625 initVirtMem
->writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsysexitOffset
,
626 vsysexitBlob
, sizeof(vsysexitBlob
));
628 for (int i
= 0; i
< contextIds
.size(); i
++) {
629 ThreadContext
* tc
= system
->threads
[contextIds
[i
]];
631 SegAttr dataAttr
= 0;
633 dataAttr
.unusable
= 0;
634 dataAttr
.defaultSize
= 1;
635 dataAttr
.longMode
= 0;
637 dataAttr
.granularity
= 1;
638 dataAttr
.present
= 1;
640 dataAttr
.writable
= 1;
641 dataAttr
.readable
= 1;
642 dataAttr
.expandDown
= 0;
645 // Initialize the segment registers.
646 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
647 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
648 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
649 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
650 tc
->setMiscRegNoEffect(MISCREG_SEG_SEL(seg
), 0xB);
651 tc
->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg
), (uint32_t)(-1));
657 csAttr
.defaultSize
= 1;
660 csAttr
.granularity
= 1;
665 csAttr
.expandDown
= 0;
668 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
670 tc
->setMiscRegNoEffect(MISCREG_TSG_BASE
, _gdtStart
);
671 tc
->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE
, _gdtStart
);
672 tc
->setMiscRegNoEffect(MISCREG_TSG_LIMIT
, _gdtStart
+ _gdtSize
- 1);
674 // Set the LDT selector to 0 to deactivate it.
675 tc
->setMiscRegNoEffect(MISCREG_TSL
, 0);
678 efer
.sce
= 1; // Enable system call extensions.
679 efer
.lme
= 1; // Enable long mode.
680 efer
.lma
= 0; // Deactivate long mode.
681 efer
.nxe
= 1; // Enable nx support.
682 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
683 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
684 tc
->setMiscReg(MISCREG_EFER
, efer
);
686 // Set up the registers that describe the operating mode.
688 cr0
.pg
= 1; // Turn on paging.
689 cr0
.cd
= 0; // Don't disable caching.
690 cr0
.nw
= 0; // This is bit is defined to be ignored.
691 cr0
.am
= 0; // No alignment checking
692 cr0
.wp
= 0; // Supervisor mode can write read only pages
694 cr0
.et
= 1; // This should always be 1
695 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
696 // would be pointless.
697 cr0
.em
= 0; // Allow x87 instructions to execute natively.
698 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
699 // setting it to one.
700 cr0
.pe
= 1; // We're definitely in protected mode.
701 tc
->setMiscReg(MISCREG_CR0
, cr0
);
703 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
707 template<class IntType
>
709 X86Process::argsInit(int pageSize
,
710 std::vector
<AuxVector
<IntType
> > extraAuxvs
)
712 int intSize
= sizeof(IntType
);
714 std::vector
<AuxVector
<IntType
>> auxv
= extraAuxvs
;
722 // We want 16 byte alignment
726 X86_OnboardFPU
= 1 << 0,
727 X86_VirtualModeExtensions
= 1 << 1,
728 X86_DebuggingExtensions
= 1 << 2,
729 X86_PageSizeExtensions
= 1 << 3,
731 X86_TimeStampCounter
= 1 << 4,
732 X86_ModelSpecificRegisters
= 1 << 5,
733 X86_PhysicalAddressExtensions
= 1 << 6,
734 X86_MachineCheckExtensions
= 1 << 7,
736 X86_CMPXCHG8Instruction
= 1 << 8,
737 X86_OnboardAPIC
= 1 << 9,
738 X86_SYSENTER_SYSEXIT
= 1 << 11,
740 X86_MemoryTypeRangeRegisters
= 1 << 12,
741 X86_PageGlobalEnable
= 1 << 13,
742 X86_MachineCheckArchitecture
= 1 << 14,
743 X86_CMOVInstruction
= 1 << 15,
745 X86_PageAttributeTable
= 1 << 16,
746 X86_36BitPSEs
= 1 << 17,
747 X86_ProcessorSerialNumber
= 1 << 18,
748 X86_CLFLUSHInstruction
= 1 << 19,
750 X86_DebugTraceStore
= 1 << 21,
751 X86_ACPIViaMSR
= 1 << 22,
752 X86_MultimediaExtensions
= 1 << 23,
754 X86_FXSAVE_FXRSTOR
= 1 << 24,
755 X86_StreamingSIMDExtensions
= 1 << 25,
756 X86_StreamingSIMDExtensions2
= 1 << 26,
757 X86_CPUSelfSnoop
= 1 << 27,
759 X86_HyperThreading
= 1 << 28,
760 X86_AutomaticClockControl
= 1 << 29,
761 X86_IA64Processor
= 1 << 30
764 // Setup the auxiliary vectors. These will already have endian
765 // conversion. Auxiliary vectors are loaded only for elf formatted
766 // executables; the auxv is responsible for passing information from
767 // the OS to the interpreter.
768 auto *elfObject
= dynamic_cast<::Loader::ElfObject
*>(objFile
);
772 X86_VirtualModeExtensions
|
773 X86_DebuggingExtensions
|
774 X86_PageSizeExtensions
|
775 X86_TimeStampCounter
|
776 X86_ModelSpecificRegisters
|
777 X86_PhysicalAddressExtensions
|
778 X86_MachineCheckExtensions
|
779 X86_CMPXCHG8Instruction
|
781 X86_SYSENTER_SYSEXIT
|
782 X86_MemoryTypeRangeRegisters
|
783 X86_PageGlobalEnable
|
784 X86_MachineCheckArchitecture
|
785 X86_CMOVInstruction
|
786 X86_PageAttributeTable
|
788 // X86_ProcessorSerialNumber |
789 X86_CLFLUSHInstruction
|
790 // X86_DebugTraceStore |
792 X86_MultimediaExtensions
|
794 X86_StreamingSIMDExtensions
|
795 X86_StreamingSIMDExtensions2
|
796 // X86_CPUSelfSnoop |
797 // X86_HyperThreading |
798 // X86_AutomaticClockControl |
799 // X86_IA64Processor |
802 // Bits which describe the system hardware capabilities
803 // XXX Figure out what these should be
804 auxv
.emplace_back(M5_AT_HWCAP
, features
);
805 // The system page size
806 auxv
.emplace_back(M5_AT_PAGESZ
, X86ISA::PageBytes
);
807 // Frequency at which times() increments
808 // Defined to be 100 in the kernel source.
809 auxv
.emplace_back(M5_AT_CLKTCK
, 100);
810 // This is the virtual address of the program header tables if they
811 // appear in the executable image.
812 auxv
.emplace_back(M5_AT_PHDR
, elfObject
->programHeaderTable());
813 // This is the size of a program header entry from the elf file.
814 auxv
.emplace_back(M5_AT_PHENT
, elfObject
->programHeaderSize());
815 // This is the number of program headers from the original elf file.
816 auxv
.emplace_back(M5_AT_PHNUM
, elfObject
->programHeaderCount());
817 // This is the base address of the ELF interpreter; it should be
818 // zero for static executables or contain the base address for
819 // dynamic executables.
820 auxv
.emplace_back(M5_AT_BASE
, getBias());
821 // XXX Figure out what this should be.
822 auxv
.emplace_back(M5_AT_FLAGS
, 0);
823 // The entry point to the program
824 auxv
.emplace_back(M5_AT_ENTRY
, objFile
->entryPoint());
825 // Different user and group IDs
826 auxv
.emplace_back(M5_AT_UID
, uid());
827 auxv
.emplace_back(M5_AT_EUID
, euid());
828 auxv
.emplace_back(M5_AT_GID
, gid());
829 auxv
.emplace_back(M5_AT_EGID
, egid());
830 // Whether to enable "secure mode" in the executable
831 auxv
.emplace_back(M5_AT_SECURE
, 0);
832 // The address of 16 "random" bytes.
833 auxv
.emplace_back(M5_AT_RANDOM
, 0);
834 // The name of the program
835 auxv
.emplace_back(M5_AT_EXECFN
, 0);
836 // The platform string
837 auxv
.emplace_back(M5_AT_PLATFORM
, 0);
840 // Figure out how big the initial stack needs to be
842 // A sentry NULL void pointer at the top of the stack.
843 int sentry_size
= intSize
;
845 // This is the name of the file which is present on the initial stack
846 // It's purpose is to let the user space linker examine the original file.
847 int file_name_size
= filename
.size() + 1;
849 const int numRandomBytes
= 16;
850 int aux_data_size
= numRandomBytes
;
852 string platform
= "x86_64";
853 aux_data_size
+= platform
.size() + 1;
855 int env_data_size
= 0;
856 for (int i
= 0; i
< envp
.size(); ++i
)
857 env_data_size
+= envp
[i
].size() + 1;
858 int arg_data_size
= 0;
859 for (int i
= 0; i
< argv
.size(); ++i
)
860 arg_data_size
+= argv
[i
].size() + 1;
862 // The info_block needs to be padded so its size is a multiple of the
863 // alignment mask. Also, it appears that there needs to be at least some
864 // padding, so if the size is already a multiple, we need to increase it
866 int base_info_block_size
=
867 sentry_size
+ file_name_size
+ env_data_size
+ arg_data_size
;
869 int info_block_size
= roundUp(base_info_block_size
, align
);
871 int info_block_padding
= info_block_size
- base_info_block_size
;
873 // Each auxiliary vector is two 8 byte words
874 int aux_array_size
= intSize
* 2 * (auxv
.size() + 1);
876 int envp_array_size
= intSize
* (envp
.size() + 1);
877 int argv_array_size
= intSize
* (argv
.size() + 1);
879 int argc_size
= intSize
;
881 // Figure out the size of the contents of the actual initial frame
888 // There needs to be padding after the auxiliary vector data so that the
889 // very bottom of the stack is aligned properly.
890 int partial_size
= frame_size
+ aux_data_size
;
891 int aligned_partial_size
= roundUp(partial_size
, align
);
892 int aux_padding
= aligned_partial_size
- partial_size
;
900 Addr stack_base
= memState
->getStackBase();
902 Addr stack_min
= stack_base
- space_needed
;
903 stack_min
= roundDown(stack_min
, align
);
905 unsigned stack_size
= stack_base
- stack_min
;
906 stack_size
= roundUp(stack_size
, pageSize
);
907 memState
->setStackSize(stack_size
);
910 Addr stack_end
= roundDown(stack_base
- stack_size
, pageSize
);
912 DPRINTF(Stack
, "Mapping the stack: 0x%x %dB\n", stack_end
, stack_size
);
913 memState
->mapRegion(stack_end
, stack_size
, "stack");
915 // map out initial stack contents
916 IntType sentry_base
= stack_base
- sentry_size
;
917 IntType file_name_base
= sentry_base
- file_name_size
;
918 IntType env_data_base
= file_name_base
- env_data_size
;
919 IntType arg_data_base
= env_data_base
- arg_data_size
;
920 IntType aux_data_base
= arg_data_base
- info_block_padding
- aux_data_size
;
921 IntType auxv_array_base
= aux_data_base
- aux_array_size
- aux_padding
;
922 IntType envp_array_base
= auxv_array_base
- envp_array_size
;
923 IntType argv_array_base
= envp_array_base
- argv_array_size
;
924 IntType argc_base
= argv_array_base
- argc_size
;
926 DPRINTF(Stack
, "The addresses of items on the initial stack:\n");
927 DPRINTF(Stack
, "0x%x - file name\n", file_name_base
);
928 DPRINTF(Stack
, "0x%x - env data\n", env_data_base
);
929 DPRINTF(Stack
, "0x%x - arg data\n", arg_data_base
);
930 DPRINTF(Stack
, "0x%x - aux data\n", aux_data_base
);
931 DPRINTF(Stack
, "0x%x - auxv array\n", auxv_array_base
);
932 DPRINTF(Stack
, "0x%x - envp array\n", envp_array_base
);
933 DPRINTF(Stack
, "0x%x - argv array\n", argv_array_base
);
934 DPRINTF(Stack
, "0x%x - argc \n", argc_base
);
935 DPRINTF(Stack
, "0x%x - stack min\n", stack_min
);
937 // write contents to stack
940 IntType argc
= argv
.size();
941 IntType guestArgc
= htole(argc
);
943 // Write out the sentry void *
944 IntType sentry_NULL
= 0;
945 initVirtMem
->writeBlob(sentry_base
, &sentry_NULL
, sentry_size
);
947 // Write the file name
948 initVirtMem
->writeString(file_name_base
, filename
.c_str());
950 // Fix up the aux vectors which point to data
951 assert(auxv
[auxv
.size() - 3].type
== M5_AT_RANDOM
);
952 auxv
[auxv
.size() - 3].val
= aux_data_base
;
953 assert(auxv
[auxv
.size() - 2].type
== M5_AT_EXECFN
);
954 auxv
[auxv
.size() - 2].val
= argv_array_base
;
955 assert(auxv
[auxv
.size() - 1].type
== M5_AT_PLATFORM
);
956 auxv
[auxv
.size() - 1].val
= aux_data_base
+ numRandomBytes
;
959 // Copy the aux stuff
960 Addr auxv_array_end
= auxv_array_base
;
961 for (const auto &aux
: auxv
) {
962 initVirtMem
->write(auxv_array_end
, aux
, GuestByteOrder
);
963 auxv_array_end
+= sizeof(aux
);
965 // Write out the terminating zeroed auxiliary vector
966 const AuxVector
<uint64_t> zero(0, 0);
967 initVirtMem
->write(auxv_array_end
, zero
);
968 auxv_array_end
+= sizeof(zero
);
970 initVirtMem
->writeString(aux_data_base
, platform
.c_str());
972 copyStringArray(envp
, envp_array_base
, env_data_base
,
973 ByteOrder::little
, *initVirtMem
);
974 copyStringArray(argv
, argv_array_base
, arg_data_base
,
975 ByteOrder::little
, *initVirtMem
);
977 initVirtMem
->writeBlob(argc_base
, &guestArgc
, intSize
);
979 ThreadContext
*tc
= system
->threads
[contextIds
[0]];
980 // Set the stack pointer register
981 tc
->setIntReg(StackPointerReg
, stack_min
);
983 // There doesn't need to be any segment base added in since we're dealing
984 // with the flat segmentation model.
985 tc
->pcState(getStartPC());
987 // Align the "stack_min" to a page boundary.
988 memState
->setStackMin(roundDown(stack_min
, pageSize
));
992 X86_64Process::argsInit(int pageSize
)
994 std::vector
<AuxVector
<uint64_t> > extraAuxvs
;
995 extraAuxvs
.emplace_back(M5_AT_SYSINFO_EHDR
, vsyscallPage
.base
);
996 X86Process::argsInit
<uint64_t>(pageSize
, extraAuxvs
);
1000 I386Process::argsInit(int pageSize
)
1002 std::vector
<AuxVector
<uint32_t> > extraAuxvs
;
1003 //Tell the binary where the vsyscall part of the vsyscall page is.
1004 extraAuxvs
.emplace_back(M5_AT_SYSINFO
,
1005 vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
);
1006 extraAuxvs
.emplace_back(M5_AT_SYSINFO_EHDR
, vsyscallPage
.base
);
1007 X86Process::argsInit
<uint32_t>(pageSize
, extraAuxvs
);
1011 X86_64Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1012 Process
*p
, RegVal flags
)
1014 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1015 ((X86_64Process
*)p
)->vsyscallPage
= vsyscallPage
;
1019 I386Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1020 Process
*p
, RegVal flags
)
1022 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1023 ((I386Process
*)p
)->vsyscallPage
= vsyscallPage
;