2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 #include "arch/x86/process.hh"
50 #include "arch/x86/isa_traits.hh"
51 #include "arch/x86/regs/misc.hh"
52 #include "arch/x86/regs/segment.hh"
53 #include "arch/x86/system.hh"
54 #include "arch/x86/types.hh"
55 #include "base/loader/elf_object.hh"
56 #include "base/loader/object_file.hh"
57 #include "base/logging.hh"
58 #include "base/trace.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/Stack.hh"
61 #include "mem/multi_level_page_table.hh"
62 #include "mem/page_table.hh"
63 #include "params/Process.hh"
64 #include "sim/aux_vector.hh"
65 #include "sim/process_impl.hh"
66 #include "sim/syscall_desc.hh"
67 #include "sim/syscall_return.hh"
68 #include "sim/system.hh"
71 using namespace X86ISA
;
73 static const int ArgumentReg
[] = {
77 // This argument register is r10 for syscalls and rcx for C.
84 static const int NumArgumentRegs M5_VAR_USED
=
85 sizeof(ArgumentReg
) / sizeof(const int);
87 static const int ArgumentReg32
[] = {
96 static const int NumArgumentRegs32 M5_VAR_USED
=
97 sizeof(ArgumentReg
) / sizeof(const int);
99 template class MultiLevelPageTable
<LongModePTE
<47, 39>,
102 LongModePTE
<20, 12> >;
103 typedef MultiLevelPageTable
<LongModePTE
<47, 39>,
106 LongModePTE
<20, 12> > ArchPageTable
;
108 X86Process::X86Process(ProcessParams
*params
, ObjectFile
*objFile
,
109 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
110 : Process(params
, params
->useArchPT
?
111 static_cast<EmulationPageTable
*>(
112 new ArchPageTable(params
->name
, params
->pid
,
113 params
->system
, PageBytes
)) :
114 new EmulationPageTable(params
->name
, params
->pid
,
117 syscallDescs(_syscallDescs
), numSyscallDescs(_numSyscallDescs
)
121 void X86Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
122 Process
*p
, RegVal flags
)
124 Process::clone(old_tc
, new_tc
, p
, flags
);
125 X86Process
*process
= (X86Process
*)p
;
129 X86_64Process::X86_64Process(ProcessParams
*params
, ObjectFile
*objFile
,
130 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
131 : X86Process(params
, objFile
, _syscallDescs
, _numSyscallDescs
)
134 vsyscallPage
.base
= 0xffffffffff600000ULL
;
135 vsyscallPage
.size
= PageBytes
;
136 vsyscallPage
.vtimeOffset
= 0x400;
137 vsyscallPage
.vgettimeofdayOffset
= 0x0;
139 Addr brk_point
= roundUp(image
.maxAddr(), PageBytes
);
140 Addr stack_base
= 0x7FFFFFFFF000ULL
;
141 Addr max_stack_size
= 8 * 1024 * 1024;
142 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
143 Addr mmap_end
= 0x7FFFF7FFF000ULL
;
145 memState
= make_shared
<MemState
>(brk_point
, stack_base
, max_stack_size
,
146 next_thread_stack_base
, mmap_end
);
150 I386Process::I386Process(ProcessParams
*params
, ObjectFile
*objFile
,
151 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
152 : X86Process(params
, objFile
, _syscallDescs
, _numSyscallDescs
)
155 panic("KVM CPU model does not support 32 bit processes");
157 _gdtStart
= ULL(0xffffd000);
158 _gdtSize
= PageBytes
;
160 vsyscallPage
.base
= 0xffffe000ULL
;
161 vsyscallPage
.size
= PageBytes
;
162 vsyscallPage
.vsyscallOffset
= 0x400;
163 vsyscallPage
.vsysexitOffset
= 0x410;
165 Addr brk_point
= roundUp(image
.maxAddr(), PageBytes
);
166 Addr stack_base
= _gdtStart
;
167 Addr max_stack_size
= 8 * 1024 * 1024;
168 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
169 Addr mmap_end
= 0xB7FFF000ULL
;
171 memState
= make_shared
<MemState
>(brk_point
, stack_base
, max_stack_size
,
172 next_thread_stack_base
, mmap_end
);
176 X86Process::getDesc(int callnum
)
178 if (callnum
< 0 || callnum
>= numSyscallDescs
)
180 return &syscallDescs
[callnum
];
184 X86_64Process::initState()
186 X86Process::initState();
193 // Set up the vsyscall page for this process.
194 allocateMem(vsyscallPage
.base
, vsyscallPage
.size
);
195 uint8_t vtimeBlob
[] = {
196 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
197 0x0f,0x05, // syscall
200 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vtimeOffset
,
201 vtimeBlob
, sizeof(vtimeBlob
));
203 uint8_t vgettimeofdayBlob
[] = {
204 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
205 0x0f,0x05, // syscall
208 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vgettimeofdayOffset
,
209 vgettimeofdayBlob
, sizeof(vgettimeofdayBlob
));
212 PortProxy physProxy
= system
->physProxy
;
214 Addr syscallCodePhysAddr
= system
->allocPhysPages(1);
215 Addr gdtPhysAddr
= system
->allocPhysPages(1);
216 Addr idtPhysAddr
= system
->allocPhysPages(1);
217 Addr istPhysAddr
= system
->allocPhysPages(1);
218 Addr tssPhysAddr
= system
->allocPhysPages(1);
219 Addr pfHandlerPhysAddr
= system
->allocPhysPages(1);
224 uint8_t numGDTEntries
= 0;
225 uint64_t nullDescriptor
= 0;
226 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
230 SegDescriptor initDesc
= 0;
231 initDesc
.type
.codeOrData
= 0; // code or data type
232 initDesc
.type
.c
= 0; // conforming
233 initDesc
.type
.r
= 1; // readable
234 initDesc
.dpl
= 0; // privilege
235 initDesc
.p
= 1; // present
236 initDesc
.l
= 1; // longmode - 64 bit
237 initDesc
.d
= 0; // operand size
239 initDesc
.s
= 1; // system segment
240 initDesc
.limit
= 0xFFFFFFFF;
243 //64 bit code segment
244 SegDescriptor csLowPLDesc
= initDesc
;
245 csLowPLDesc
.type
.codeOrData
= 1;
247 uint64_t csLowPLDescVal
= csLowPLDesc
;
248 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
253 SegSelector csLowPL
= 0;
254 csLowPL
.si
= numGDTEntries
- 1;
257 //64 bit data segment
258 SegDescriptor dsLowPLDesc
= initDesc
;
259 dsLowPLDesc
.type
.codeOrData
= 0;
261 uint64_t dsLowPLDescVal
= dsLowPLDesc
;
262 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
267 SegSelector dsLowPL
= 0;
268 dsLowPL
.si
= numGDTEntries
- 1;
271 //64 bit data segment
272 SegDescriptor dsDesc
= initDesc
;
273 dsDesc
.type
.codeOrData
= 0;
275 uint64_t dsDescVal
= dsDesc
;
276 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
282 ds
.si
= numGDTEntries
- 1;
285 //64 bit code segment
286 SegDescriptor csDesc
= initDesc
;
287 csDesc
.type
.codeOrData
= 1;
289 uint64_t csDescVal
= csDesc
;
290 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
296 cs
.si
= numGDTEntries
- 1;
299 SegSelector scall
= 0;
300 scall
.si
= csLowPL
.si
;
303 SegSelector sret
= 0;
304 sret
.si
= dsLowPL
.si
;
307 /* In long mode the TSS has been extended to 16 Bytes */
308 TSSlow TSSDescLow
= 0;
309 TSSDescLow
.type
= 0xB;
310 TSSDescLow
.dpl
= 0; // Privelege level 0
311 TSSDescLow
.p
= 1; // Present
312 TSSDescLow
.limit
= 0xFFFFFFFF;
313 TSSDescLow
.base
= bits(TSSVirtAddr
, 31, 0);
315 TSShigh TSSDescHigh
= 0;
316 TSSDescHigh
.base
= bits(TSSVirtAddr
, 63, 32);
321 } tssDescVal
= {TSSDescLow
, TSSDescHigh
};
323 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
324 &tssDescVal
, sizeof(tssDescVal
));
328 SegSelector tssSel
= 0;
329 tssSel
.si
= numGDTEntries
- 1;
331 uint64_t tss_base_addr
= (TSSDescHigh
.base
<< 32) | TSSDescLow
.base
;
332 uint64_t tss_limit
= TSSDescLow
.limit
;
334 SegAttr tss_attr
= 0;
336 tss_attr
.type
= TSSDescLow
.type
;
337 tss_attr
.dpl
= TSSDescLow
.dpl
;
338 tss_attr
.present
= TSSDescLow
.p
;
339 tss_attr
.granularity
= TSSDescLow
.g
;
340 tss_attr
.unusable
= 0;
342 for (int i
= 0; i
< contextIds
.size(); i
++) {
343 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
345 tc
->setMiscReg(MISCREG_CS
, cs
);
346 tc
->setMiscReg(MISCREG_DS
, ds
);
347 tc
->setMiscReg(MISCREG_ES
, ds
);
348 tc
->setMiscReg(MISCREG_FS
, ds
);
349 tc
->setMiscReg(MISCREG_GS
, ds
);
350 tc
->setMiscReg(MISCREG_SS
, ds
);
353 tc
->setMiscReg(MISCREG_TSL
, 0);
357 tc
->setMiscReg(MISCREG_TSL_ATTR
, tslAttr
);
359 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
360 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 8 * numGDTEntries
- 1);
362 tc
->setMiscReg(MISCREG_TR
, tssSel
);
363 tc
->setMiscReg(MISCREG_TR_BASE
, tss_base_addr
);
364 tc
->setMiscReg(MISCREG_TR_EFF_BASE
, 0);
365 tc
->setMiscReg(MISCREG_TR_LIMIT
, tss_limit
);
366 tc
->setMiscReg(MISCREG_TR_ATTR
, tss_attr
);
368 //Start using longmode segments.
369 installSegDesc(tc
, SEGMENT_REG_CS
, csDesc
, true);
370 installSegDesc(tc
, SEGMENT_REG_DS
, dsDesc
, true);
371 installSegDesc(tc
, SEGMENT_REG_ES
, dsDesc
, true);
372 installSegDesc(tc
, SEGMENT_REG_FS
, dsDesc
, true);
373 installSegDesc(tc
, SEGMENT_REG_GS
, dsDesc
, true);
374 installSegDesc(tc
, SEGMENT_REG_SS
, dsDesc
, true);
377 efer
.sce
= 1; // Enable system call extensions.
378 efer
.lme
= 1; // Enable long mode.
379 efer
.lma
= 1; // Activate long mode.
380 efer
.nxe
= 1; // Enable nx support.
381 efer
.svme
= 0; // Enable svm support for now.
382 efer
.ffxsr
= 0; // Turn on fast fxsave and fxrstor.
383 tc
->setMiscReg(MISCREG_EFER
, efer
);
385 //Set up the registers that describe the operating mode.
387 cr0
.pg
= 1; // Turn on paging.
388 cr0
.cd
= 0; // Don't disable caching.
389 cr0
.nw
= 0; // This is bit is defined to be ignored.
390 cr0
.am
= 1; // No alignment checking
391 cr0
.wp
= 1; // Supervisor mode can write read only pages
393 cr0
.et
= 1; // This should always be 1
394 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
395 // would be pointless.
396 cr0
.em
= 0; // Allow x87 instructions to execute natively.
397 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
398 // setting it to one.
399 cr0
.pe
= 1; // We're definitely in protected mode.
400 tc
->setMiscReg(MISCREG_CR0
, cr0
);
403 tc
->setMiscReg(MISCREG_CR2
, cr2
);
405 CR3 cr3
= dynamic_cast<ArchPageTable
*>(pTable
)->basePtr();
406 tc
->setMiscReg(MISCREG_CR3
, cr3
);
410 cr4
.osxsave
= 0; // Enable XSAVE and Proc Extended States
411 cr4
.osxmmexcpt
= 0; // Operating System Unmasked Exception
412 cr4
.osfxsr
= 1; // Operating System FXSave/FSRSTOR Support
413 cr4
.pce
= 0; // Performance-Monitoring Counter Enable
414 cr4
.pge
= 0; // Page-Global Enable
415 cr4
.mce
= 0; // Machine Check Enable
416 cr4
.pae
= 1; // Physical-Address Extension
417 cr4
.pse
= 0; // Page Size Extensions
418 cr4
.de
= 0; // Debugging Extensions
419 cr4
.tsd
= 0; // Time Stamp Disable
420 cr4
.pvi
= 0; // Protected-Mode Virtual Interrupts
421 cr4
.vme
= 0; // Virtual-8086 Mode Extensions
423 tc
->setMiscReg(MISCREG_CR4
, cr4
);
426 tc
->setMiscReg(MISCREG_CR8
, cr8
);
428 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
430 tc
->setMiscReg(MISCREG_APIC_BASE
, 0xfee00900);
432 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
433 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 0xffff);
435 tc
->setMiscReg(MISCREG_IDTR_BASE
, IDTVirtAddr
);
436 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
438 /* enabling syscall and sysret */
439 RegVal star
= ((RegVal
)sret
<< 48) | ((RegVal
)scall
<< 32);
440 tc
->setMiscReg(MISCREG_STAR
, star
);
441 RegVal lstar
= (RegVal
)syscallCodeVirtAddr
;
442 tc
->setMiscReg(MISCREG_LSTAR
, lstar
);
443 RegVal sfmask
= (1 << 8) | (1 << 10); // TF | DF
444 tc
->setMiscReg(MISCREG_SF_MASK
, sfmask
);
447 /* Set up the content of the TSS and write it to physical memory. */
450 uint32_t reserved0
; // +00h
451 uint32_t RSP0_low
; // +04h
452 uint32_t RSP0_high
; // +08h
453 uint32_t RSP1_low
; // +0Ch
454 uint32_t RSP1_high
; // +10h
455 uint32_t RSP2_low
; // +14h
456 uint32_t RSP2_high
; // +18h
457 uint32_t reserved1
; // +1Ch
458 uint32_t reserved2
; // +20h
459 uint32_t IST1_low
; // +24h
460 uint32_t IST1_high
; // +28h
461 uint32_t IST2_low
; // +2Ch
462 uint32_t IST2_high
; // +30h
463 uint32_t IST3_low
; // +34h
464 uint32_t IST3_high
; // +38h
465 uint32_t IST4_low
; // +3Ch
466 uint32_t IST4_high
; // +40h
467 uint32_t IST5_low
; // +44h
468 uint32_t IST5_high
; // +48h
469 uint32_t IST6_low
; // +4Ch
470 uint32_t IST6_high
; // +50h
471 uint32_t IST7_low
; // +54h
472 uint32_t IST7_high
; // +58h
473 uint32_t reserved3
; // +5Ch
474 uint32_t reserved4
; // +60h
475 uint16_t reserved5
; // +64h
476 uint16_t IO_MapBase
; // +66h
479 /** setting Interrupt Stack Table */
480 uint64_t IST_start
= ISTVirtAddr
+ PageBytes
;
481 tss
.IST1_low
= IST_start
;
482 tss
.IST1_high
= IST_start
>> 32;
483 tss
.RSP0_low
= tss
.IST1_low
;
484 tss
.RSP0_high
= tss
.IST1_high
;
485 tss
.RSP1_low
= tss
.IST1_low
;
486 tss
.RSP1_high
= tss
.IST1_high
;
487 tss
.RSP2_low
= tss
.IST1_low
;
488 tss
.RSP2_high
= tss
.IST1_high
;
489 physProxy
.writeBlob(tssPhysAddr
, &tss
, sizeof(tss
));
491 /* Setting IDT gates */
492 GateDescriptorLow PFGateLow
= 0;
493 PFGateLow
.offsetHigh
= bits(PFHandlerVirtAddr
, 31, 16);
494 PFGateLow
.offsetLow
= bits(PFHandlerVirtAddr
, 15, 0);
495 PFGateLow
.selector
= csLowPL
;
498 PFGateLow
.type
= 0xe; // gate interrupt type
499 PFGateLow
.IST
= 0; // setting IST to 0 and using RSP0
501 GateDescriptorHigh PFGateHigh
= 0;
502 PFGateHigh
.offset
= bits(PFHandlerVirtAddr
, 63, 32);
507 } PFGate
= {PFGateLow
, PFGateHigh
};
509 physProxy
.writeBlob(idtPhysAddr
+ 0xE0, &PFGate
, sizeof(PFGate
));
511 /* System call handler */
512 uint8_t syscallBlob
[] = {
513 // mov %rax, (0xffffc90000005600)
514 0x48, 0xa3, 0x00, 0x60, 0x00,
515 0x00, 0x00, 0xc9, 0xff, 0xff,
520 physProxy
.writeBlob(syscallCodePhysAddr
,
521 syscallBlob
, sizeof(syscallBlob
));
523 /** Page fault handler */
524 uint8_t faultBlob
[] = {
525 // mov %rax, (0xffffc90000005700)
526 0x48, 0xa3, 0x00, 0x61, 0x00,
527 0x00, 0x00, 0xc9, 0xff, 0xff,
528 // add $0x8, %rsp # skip error
529 0x48, 0x83, 0xc4, 0x08,
534 physProxy
.writeBlob(pfHandlerPhysAddr
, faultBlob
, sizeof(faultBlob
));
536 /* Syscall handler */
537 pTable
->map(syscallCodeVirtAddr
, syscallCodePhysAddr
,
540 pTable
->map(GDTVirtAddr
, gdtPhysAddr
, PageBytes
, false);
542 pTable
->map(IDTVirtAddr
, idtPhysAddr
, PageBytes
, false);
544 pTable
->map(TSSVirtAddr
, tssPhysAddr
, PageBytes
, false);
546 pTable
->map(ISTVirtAddr
, istPhysAddr
, PageBytes
, false);
548 pTable
->map(PFHandlerVirtAddr
, pfHandlerPhysAddr
, PageBytes
, false);
549 /* MMIO region for m5ops */
550 pTable
->map(MMIORegionVirtAddr
, MMIORegionPhysAddr
,
551 16 * PageBytes
, false);
553 for (int i
= 0; i
< contextIds
.size(); i
++) {
554 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
556 SegAttr dataAttr
= 0;
558 dataAttr
.unusable
= 0;
559 dataAttr
.defaultSize
= 1;
560 dataAttr
.longMode
= 1;
562 dataAttr
.granularity
= 1;
563 dataAttr
.present
= 1;
565 dataAttr
.writable
= 1;
566 dataAttr
.readable
= 1;
567 dataAttr
.expandDown
= 0;
570 // Initialize the segment registers.
571 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
572 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
573 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
574 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
580 csAttr
.defaultSize
= 0;
583 csAttr
.granularity
= 1;
588 csAttr
.expandDown
= 0;
591 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
594 efer
.sce
= 1; // Enable system call extensions.
595 efer
.lme
= 1; // Enable long mode.
596 efer
.lma
= 1; // Activate long mode.
597 efer
.nxe
= 1; // Enable nx support.
598 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
599 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
600 tc
->setMiscReg(MISCREG_EFER
, efer
);
602 // Set up the registers that describe the operating mode.
604 cr0
.pg
= 1; // Turn on paging.
605 cr0
.cd
= 0; // Don't disable caching.
606 cr0
.nw
= 0; // This is bit is defined to be ignored.
607 cr0
.am
= 0; // No alignment checking
608 cr0
.wp
= 0; // Supervisor mode can write read only pages
610 cr0
.et
= 1; // This should always be 1
611 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
612 // would be pointless.
613 cr0
.em
= 0; // Allow x87 instructions to execute natively.
614 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
615 // setting it to one.
616 cr0
.pe
= 1; // We're definitely in protected mode.
617 tc
->setMiscReg(MISCREG_CR0
, cr0
);
619 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
625 I386Process::initState()
627 X86Process::initState();
632 * Set up a GDT for this process. The whole GDT wouldn't really be for
633 * this process, but the only parts we care about are.
635 allocateMem(_gdtStart
, _gdtSize
);
637 assert(_gdtSize
% sizeof(zero
) == 0);
638 for (Addr gdtCurrent
= _gdtStart
;
639 gdtCurrent
< _gdtStart
+ _gdtSize
; gdtCurrent
+= sizeof(zero
)) {
640 initVirtMem
.write(gdtCurrent
, zero
);
643 // Set up the vsyscall page for this process.
644 allocateMem(vsyscallPage
.base
, vsyscallPage
.size
);
645 uint8_t vsyscallBlob
[] = {
649 0x89, 0xe5, // mov %esp, %ebp
650 0x0f, 0x34 // sysenter
652 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
,
653 vsyscallBlob
, sizeof(vsyscallBlob
));
655 uint8_t vsysexitBlob
[] = {
661 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsysexitOffset
,
662 vsysexitBlob
, sizeof(vsysexitBlob
));
664 for (int i
= 0; i
< contextIds
.size(); i
++) {
665 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
667 SegAttr dataAttr
= 0;
669 dataAttr
.unusable
= 0;
670 dataAttr
.defaultSize
= 1;
671 dataAttr
.longMode
= 0;
673 dataAttr
.granularity
= 1;
674 dataAttr
.present
= 1;
676 dataAttr
.writable
= 1;
677 dataAttr
.readable
= 1;
678 dataAttr
.expandDown
= 0;
681 // Initialize the segment registers.
682 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
683 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
684 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
685 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
686 tc
->setMiscRegNoEffect(MISCREG_SEG_SEL(seg
), 0xB);
687 tc
->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg
), (uint32_t)(-1));
693 csAttr
.defaultSize
= 1;
696 csAttr
.granularity
= 1;
701 csAttr
.expandDown
= 0;
704 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
706 tc
->setMiscRegNoEffect(MISCREG_TSG_BASE
, _gdtStart
);
707 tc
->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE
, _gdtStart
);
708 tc
->setMiscRegNoEffect(MISCREG_TSG_LIMIT
, _gdtStart
+ _gdtSize
- 1);
710 // Set the LDT selector to 0 to deactivate it.
711 tc
->setMiscRegNoEffect(MISCREG_TSL
, 0);
714 efer
.sce
= 1; // Enable system call extensions.
715 efer
.lme
= 1; // Enable long mode.
716 efer
.lma
= 0; // Deactivate long mode.
717 efer
.nxe
= 1; // Enable nx support.
718 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
719 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
720 tc
->setMiscReg(MISCREG_EFER
, efer
);
722 // Set up the registers that describe the operating mode.
724 cr0
.pg
= 1; // Turn on paging.
725 cr0
.cd
= 0; // Don't disable caching.
726 cr0
.nw
= 0; // This is bit is defined to be ignored.
727 cr0
.am
= 0; // No alignment checking
728 cr0
.wp
= 0; // Supervisor mode can write read only pages
730 cr0
.et
= 1; // This should always be 1
731 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
732 // would be pointless.
733 cr0
.em
= 0; // Allow x87 instructions to execute natively.
734 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
735 // setting it to one.
736 cr0
.pe
= 1; // We're definitely in protected mode.
737 tc
->setMiscReg(MISCREG_CR0
, cr0
);
739 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
743 template<class IntType
>
745 X86Process::argsInit(int pageSize
,
746 std::vector
<AuxVector
<IntType
> > extraAuxvs
)
748 int intSize
= sizeof(IntType
);
750 std::vector
<AuxVector
<IntType
>> auxv
= extraAuxvs
;
758 // We want 16 byte alignment
762 X86_OnboardFPU
= 1 << 0,
763 X86_VirtualModeExtensions
= 1 << 1,
764 X86_DebuggingExtensions
= 1 << 2,
765 X86_PageSizeExtensions
= 1 << 3,
767 X86_TimeStampCounter
= 1 << 4,
768 X86_ModelSpecificRegisters
= 1 << 5,
769 X86_PhysicalAddressExtensions
= 1 << 6,
770 X86_MachineCheckExtensions
= 1 << 7,
772 X86_CMPXCHG8Instruction
= 1 << 8,
773 X86_OnboardAPIC
= 1 << 9,
774 X86_SYSENTER_SYSEXIT
= 1 << 11,
776 X86_MemoryTypeRangeRegisters
= 1 << 12,
777 X86_PageGlobalEnable
= 1 << 13,
778 X86_MachineCheckArchitecture
= 1 << 14,
779 X86_CMOVInstruction
= 1 << 15,
781 X86_PageAttributeTable
= 1 << 16,
782 X86_36BitPSEs
= 1 << 17,
783 X86_ProcessorSerialNumber
= 1 << 18,
784 X86_CLFLUSHInstruction
= 1 << 19,
786 X86_DebugTraceStore
= 1 << 21,
787 X86_ACPIViaMSR
= 1 << 22,
788 X86_MultimediaExtensions
= 1 << 23,
790 X86_FXSAVE_FXRSTOR
= 1 << 24,
791 X86_StreamingSIMDExtensions
= 1 << 25,
792 X86_StreamingSIMDExtensions2
= 1 << 26,
793 X86_CPUSelfSnoop
= 1 << 27,
795 X86_HyperThreading
= 1 << 28,
796 X86_AutomaticClockControl
= 1 << 29,
797 X86_IA64Processor
= 1 << 30
800 // Setup the auxiliary vectors. These will already have endian
801 // conversion. Auxiliary vectors are loaded only for elf formatted
802 // executables; the auxv is responsible for passing information from
803 // the OS to the interpreter.
804 ElfObject
* elfObject
= dynamic_cast<ElfObject
*>(objFile
);
808 X86_VirtualModeExtensions
|
809 X86_DebuggingExtensions
|
810 X86_PageSizeExtensions
|
811 X86_TimeStampCounter
|
812 X86_ModelSpecificRegisters
|
813 X86_PhysicalAddressExtensions
|
814 X86_MachineCheckExtensions
|
815 X86_CMPXCHG8Instruction
|
817 X86_SYSENTER_SYSEXIT
|
818 X86_MemoryTypeRangeRegisters
|
819 X86_PageGlobalEnable
|
820 X86_MachineCheckArchitecture
|
821 X86_CMOVInstruction
|
822 X86_PageAttributeTable
|
824 // X86_ProcessorSerialNumber |
825 X86_CLFLUSHInstruction
|
826 // X86_DebugTraceStore |
828 X86_MultimediaExtensions
|
830 X86_StreamingSIMDExtensions
|
831 X86_StreamingSIMDExtensions2
|
832 // X86_CPUSelfSnoop |
833 // X86_HyperThreading |
834 // X86_AutomaticClockControl |
835 // X86_IA64Processor |
838 // Bits which describe the system hardware capabilities
839 // XXX Figure out what these should be
840 auxv
.emplace_back(M5_AT_HWCAP
, features
);
841 // The system page size
842 auxv
.emplace_back(M5_AT_PAGESZ
, X86ISA::PageBytes
);
843 // Frequency at which times() increments
844 // Defined to be 100 in the kernel source.
845 auxv
.emplace_back(M5_AT_CLKTCK
, 100);
846 // This is the virtual address of the program header tables if they
847 // appear in the executable image.
848 auxv
.emplace_back(M5_AT_PHDR
, elfObject
->programHeaderTable());
849 // This is the size of a program header entry from the elf file.
850 auxv
.emplace_back(M5_AT_PHENT
, elfObject
->programHeaderSize());
851 // This is the number of program headers from the original elf file.
852 auxv
.emplace_back(M5_AT_PHNUM
, elfObject
->programHeaderCount());
853 // This is the base address of the ELF interpreter; it should be
854 // zero for static executables or contain the base address for
855 // dynamic executables.
856 auxv
.emplace_back(M5_AT_BASE
, getBias());
857 // XXX Figure out what this should be.
858 auxv
.emplace_back(M5_AT_FLAGS
, 0);
859 // The entry point to the program
860 auxv
.emplace_back(M5_AT_ENTRY
, objFile
->entryPoint());
861 // Different user and group IDs
862 auxv
.emplace_back(M5_AT_UID
, uid());
863 auxv
.emplace_back(M5_AT_EUID
, euid());
864 auxv
.emplace_back(M5_AT_GID
, gid());
865 auxv
.emplace_back(M5_AT_EGID
, egid());
866 // Whether to enable "secure mode" in the executable
867 auxv
.emplace_back(M5_AT_SECURE
, 0);
868 // The address of 16 "random" bytes.
869 auxv
.emplace_back(M5_AT_RANDOM
, 0);
870 // The name of the program
871 auxv
.emplace_back(M5_AT_EXECFN
, 0);
872 // The platform string
873 auxv
.emplace_back(M5_AT_PLATFORM
, 0);
876 // Figure out how big the initial stack needs to be
878 // A sentry NULL void pointer at the top of the stack.
879 int sentry_size
= intSize
;
881 // This is the name of the file which is present on the initial stack
882 // It's purpose is to let the user space linker examine the original file.
883 int file_name_size
= filename
.size() + 1;
885 const int numRandomBytes
= 16;
886 int aux_data_size
= numRandomBytes
;
888 string platform
= "x86_64";
889 aux_data_size
+= platform
.size() + 1;
891 int env_data_size
= 0;
892 for (int i
= 0; i
< envp
.size(); ++i
)
893 env_data_size
+= envp
[i
].size() + 1;
894 int arg_data_size
= 0;
895 for (int i
= 0; i
< argv
.size(); ++i
)
896 arg_data_size
+= argv
[i
].size() + 1;
898 // The info_block needs to be padded so its size is a multiple of the
899 // alignment mask. Also, it appears that there needs to be at least some
900 // padding, so if the size is already a multiple, we need to increase it
902 int base_info_block_size
=
903 sentry_size
+ file_name_size
+ env_data_size
+ arg_data_size
;
905 int info_block_size
= roundUp(base_info_block_size
, align
);
907 int info_block_padding
= info_block_size
- base_info_block_size
;
909 // Each auxiliary vector is two 8 byte words
910 int aux_array_size
= intSize
* 2 * (auxv
.size() + 1);
912 int envp_array_size
= intSize
* (envp
.size() + 1);
913 int argv_array_size
= intSize
* (argv
.size() + 1);
915 int argc_size
= intSize
;
917 // Figure out the size of the contents of the actual initial frame
924 // There needs to be padding after the auxiliary vector data so that the
925 // very bottom of the stack is aligned properly.
926 int partial_size
= frame_size
+ aux_data_size
;
927 int aligned_partial_size
= roundUp(partial_size
, align
);
928 int aux_padding
= aligned_partial_size
- partial_size
;
936 Addr stack_base
= memState
->getStackBase();
938 Addr stack_min
= stack_base
- space_needed
;
939 stack_min
= roundDown(stack_min
, align
);
941 unsigned stack_size
= stack_base
- stack_min
;
942 stack_size
= roundUp(stack_size
, pageSize
);
943 memState
->setStackSize(stack_size
);
946 Addr stack_end
= roundDown(stack_base
- stack_size
, pageSize
);
948 DPRINTF(Stack
, "Mapping the stack: 0x%x %dB\n", stack_end
, stack_size
);
949 allocateMem(stack_end
, stack_size
);
951 // map out initial stack contents
952 IntType sentry_base
= stack_base
- sentry_size
;
953 IntType file_name_base
= sentry_base
- file_name_size
;
954 IntType env_data_base
= file_name_base
- env_data_size
;
955 IntType arg_data_base
= env_data_base
- arg_data_size
;
956 IntType aux_data_base
= arg_data_base
- info_block_padding
- aux_data_size
;
957 IntType auxv_array_base
= aux_data_base
- aux_array_size
- aux_padding
;
958 IntType envp_array_base
= auxv_array_base
- envp_array_size
;
959 IntType argv_array_base
= envp_array_base
- argv_array_size
;
960 IntType argc_base
= argv_array_base
- argc_size
;
962 DPRINTF(Stack
, "The addresses of items on the initial stack:\n");
963 DPRINTF(Stack
, "0x%x - file name\n", file_name_base
);
964 DPRINTF(Stack
, "0x%x - env data\n", env_data_base
);
965 DPRINTF(Stack
, "0x%x - arg data\n", arg_data_base
);
966 DPRINTF(Stack
, "0x%x - aux data\n", aux_data_base
);
967 DPRINTF(Stack
, "0x%x - auxv array\n", auxv_array_base
);
968 DPRINTF(Stack
, "0x%x - envp array\n", envp_array_base
);
969 DPRINTF(Stack
, "0x%x - argv array\n", argv_array_base
);
970 DPRINTF(Stack
, "0x%x - argc \n", argc_base
);
971 DPRINTF(Stack
, "0x%x - stack min\n", stack_min
);
973 // write contents to stack
976 IntType argc
= argv
.size();
977 IntType guestArgc
= htole(argc
);
979 // Write out the sentry void *
980 IntType sentry_NULL
= 0;
981 initVirtMem
.writeBlob(sentry_base
, &sentry_NULL
, sentry_size
);
983 // Write the file name
984 initVirtMem
.writeString(file_name_base
, filename
.c_str());
986 // Fix up the aux vectors which point to data
987 assert(auxv
[auxv
.size() - 3].type
== M5_AT_RANDOM
);
988 auxv
[auxv
.size() - 3].val
= aux_data_base
;
989 assert(auxv
[auxv
.size() - 2].type
== M5_AT_EXECFN
);
990 auxv
[auxv
.size() - 2].val
= argv_array_base
;
991 assert(auxv
[auxv
.size() - 1].type
== M5_AT_PLATFORM
);
992 auxv
[auxv
.size() - 1].val
= aux_data_base
+ numRandomBytes
;
995 // Copy the aux stuff
996 Addr auxv_array_end
= auxv_array_base
;
997 for (const auto &aux
: auxv
) {
998 initVirtMem
.write(auxv_array_end
, aux
, GuestByteOrder
);
999 auxv_array_end
+= sizeof(aux
);
1001 // Write out the terminating zeroed auxiliary vector
1002 const AuxVector
<uint64_t> zero(0, 0);
1003 initVirtMem
.write(auxv_array_end
, zero
);
1004 auxv_array_end
+= sizeof(zero
);
1006 initVirtMem
.writeString(aux_data_base
, platform
.c_str());
1008 copyStringArray(envp
, envp_array_base
, env_data_base
,
1009 LittleEndianByteOrder
, initVirtMem
);
1010 copyStringArray(argv
, argv_array_base
, arg_data_base
,
1011 LittleEndianByteOrder
, initVirtMem
);
1013 initVirtMem
.writeBlob(argc_base
, &guestArgc
, intSize
);
1015 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
1016 // Set the stack pointer register
1017 tc
->setIntReg(StackPointerReg
, stack_min
);
1019 // There doesn't need to be any segment base added in since we're dealing
1020 // with the flat segmentation model.
1021 tc
->pcState(getStartPC());
1023 // Align the "stack_min" to a page boundary.
1024 memState
->setStackMin(roundDown(stack_min
, pageSize
));
1028 X86_64Process::argsInit(int pageSize
)
1030 std::vector
<AuxVector
<uint64_t> > extraAuxvs
;
1031 extraAuxvs
.emplace_back(M5_AT_SYSINFO_EHDR
, vsyscallPage
.base
);
1032 X86Process::argsInit
<uint64_t>(pageSize
, extraAuxvs
);
1036 I386Process::argsInit(int pageSize
)
1038 std::vector
<AuxVector
<uint32_t> > extraAuxvs
;
1039 //Tell the binary where the vsyscall part of the vsyscall page is.
1040 extraAuxvs
.emplace_back(M5_AT_SYSINFO
,
1041 vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
);
1042 extraAuxvs
.emplace_back(M5_AT_SYSINFO_EHDR
, vsyscallPage
.base
);
1043 X86Process::argsInit
<uint32_t>(pageSize
, extraAuxvs
);
1047 X86Process::setSyscallReturn(ThreadContext
*tc
, SyscallReturn retval
)
1049 tc
->setIntReg(INTREG_RAX
, retval
.encodedValue());
1053 X86_64Process::getSyscallArg(ThreadContext
*tc
, int &i
)
1055 assert(i
< NumArgumentRegs
);
1056 return tc
->readIntReg(ArgumentReg
[i
++]);
1060 X86_64Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1061 Process
*p
, RegVal flags
)
1063 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1064 ((X86_64Process
*)p
)->vsyscallPage
= vsyscallPage
;
1068 I386Process::getSyscallArg(ThreadContext
*tc
, int &i
)
1070 assert(i
< NumArgumentRegs32
);
1071 return tc
->readIntReg(ArgumentReg32
[i
++]);
1075 I386Process::getSyscallArg(ThreadContext
*tc
, int &i
, int width
)
1077 assert(width
== 32 || width
== 64);
1078 assert(i
< NumArgumentRegs
);
1079 uint64_t retVal
= tc
->readIntReg(ArgumentReg32
[i
++]) & mask(32);
1081 retVal
|= ((uint64_t)tc
->readIntReg(ArgumentReg
[i
++]) << 32);
1086 I386Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1087 Process
*p
, RegVal flags
)
1089 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1090 ((I386Process
*)p
)->vsyscallPage
= vsyscallPage
;