2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 #include "arch/x86/process.hh"
50 #include "arch/x86/isa_traits.hh"
51 #include "arch/x86/regs/misc.hh"
52 #include "arch/x86/regs/segment.hh"
53 #include "arch/x86/system.hh"
54 #include "arch/x86/types.hh"
55 #include "base/loader/elf_object.hh"
56 #include "base/loader/object_file.hh"
57 #include "base/logging.hh"
58 #include "base/trace.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/Stack.hh"
61 #include "mem/multi_level_page_table.hh"
62 #include "mem/page_table.hh"
63 #include "params/Process.hh"
64 #include "sim/aux_vector.hh"
65 #include "sim/process_impl.hh"
66 #include "sim/syscall_desc.hh"
67 #include "sim/syscall_return.hh"
68 #include "sim/system.hh"
71 using namespace X86ISA
;
73 static const int ArgumentReg
[] = {
77 // This argument register is r10 for syscalls and rcx for C.
84 static const int NumArgumentRegs M5_VAR_USED
=
85 sizeof(ArgumentReg
) / sizeof(const int);
87 static const int ArgumentReg32
[] = {
96 static const int NumArgumentRegs32 M5_VAR_USED
=
97 sizeof(ArgumentReg
) / sizeof(const int);
99 template class MultiLevelPageTable
<LongModePTE
<47, 39>,
102 LongModePTE
<20, 12> >;
103 typedef MultiLevelPageTable
<LongModePTE
<47, 39>,
106 LongModePTE
<20, 12> > ArchPageTable
;
108 X86Process::X86Process(ProcessParams
*params
, ObjectFile
*objFile
,
109 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
110 : Process(params
, params
->useArchPT
?
111 static_cast<EmulationPageTable
*>(
112 new ArchPageTable(params
->name
, params
->pid
,
113 params
->system
, PageBytes
)) :
114 new EmulationPageTable(params
->name
, params
->pid
,
117 syscallDescs(_syscallDescs
), numSyscallDescs(_numSyscallDescs
)
121 void X86Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
122 Process
*p
, RegVal flags
)
124 Process::clone(old_tc
, new_tc
, p
, flags
);
125 X86Process
*process
= (X86Process
*)p
;
129 X86_64Process::X86_64Process(ProcessParams
*params
, ObjectFile
*objFile
,
130 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
131 : X86Process(params
, objFile
, _syscallDescs
, _numSyscallDescs
)
134 vsyscallPage
.base
= 0xffffffffff600000ULL
;
135 vsyscallPage
.size
= PageBytes
;
136 vsyscallPage
.vtimeOffset
= 0x400;
137 vsyscallPage
.vgettimeofdayOffset
= 0x0;
139 Addr brk_point
= roundUp(objFile
->dataBase() + objFile
->dataSize() +
140 objFile
->bssSize(), PageBytes
);
141 Addr stack_base
= 0x7FFFFFFFF000ULL
;
142 Addr max_stack_size
= 8 * 1024 * 1024;
143 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
144 Addr mmap_end
= 0x7FFFF7FFF000ULL
;
146 memState
= make_shared
<MemState
>(brk_point
, stack_base
, max_stack_size
,
147 next_thread_stack_base
, mmap_end
);
151 I386Process::syscall(int64_t callnum
, ThreadContext
*tc
, Fault
*fault
)
153 PCState pc
= tc
->pcState();
155 if (eip
>= vsyscallPage
.base
&&
156 eip
< vsyscallPage
.base
+ vsyscallPage
.size
) {
157 pc
.npc(vsyscallPage
.base
+ vsyscallPage
.vsysexitOffset
);
160 X86Process::syscall(callnum
, tc
, fault
);
164 I386Process::I386Process(ProcessParams
*params
, ObjectFile
*objFile
,
165 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
166 : X86Process(params
, objFile
, _syscallDescs
, _numSyscallDescs
)
169 panic("KVM CPU model does not support 32 bit processes");
171 _gdtStart
= ULL(0xffffd000);
172 _gdtSize
= PageBytes
;
174 vsyscallPage
.base
= 0xffffe000ULL
;
175 vsyscallPage
.size
= PageBytes
;
176 vsyscallPage
.vsyscallOffset
= 0x400;
177 vsyscallPage
.vsysexitOffset
= 0x410;
179 Addr brk_point
= roundUp(objFile
->dataBase() + objFile
->dataSize() +
180 objFile
->bssSize(), PageBytes
);
181 Addr stack_base
= _gdtStart
;
182 Addr max_stack_size
= 8 * 1024 * 1024;
183 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
184 Addr mmap_end
= 0xB7FFF000ULL
;
186 memState
= make_shared
<MemState
>(brk_point
, stack_base
, max_stack_size
,
187 next_thread_stack_base
, mmap_end
);
191 X86Process::getDesc(int callnum
)
193 if (callnum
< 0 || callnum
>= numSyscallDescs
)
195 return &syscallDescs
[callnum
];
199 X86_64Process::initState()
201 X86Process::initState();
208 // Set up the vsyscall page for this process.
209 allocateMem(vsyscallPage
.base
, vsyscallPage
.size
);
210 uint8_t vtimeBlob
[] = {
211 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
212 0x0f,0x05, // syscall
215 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vtimeOffset
,
216 vtimeBlob
, sizeof(vtimeBlob
));
218 uint8_t vgettimeofdayBlob
[] = {
219 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
220 0x0f,0x05, // syscall
223 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vgettimeofdayOffset
,
224 vgettimeofdayBlob
, sizeof(vgettimeofdayBlob
));
227 PortProxy physProxy
= system
->physProxy
;
229 Addr syscallCodePhysAddr
= system
->allocPhysPages(1);
230 Addr gdtPhysAddr
= system
->allocPhysPages(1);
231 Addr idtPhysAddr
= system
->allocPhysPages(1);
232 Addr istPhysAddr
= system
->allocPhysPages(1);
233 Addr tssPhysAddr
= system
->allocPhysPages(1);
234 Addr pfHandlerPhysAddr
= system
->allocPhysPages(1);
239 uint8_t numGDTEntries
= 0;
240 uint64_t nullDescriptor
= 0;
241 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
242 (uint8_t *)(&nullDescriptor
), 8);
245 SegDescriptor initDesc
= 0;
246 initDesc
.type
.codeOrData
= 0; // code or data type
247 initDesc
.type
.c
= 0; // conforming
248 initDesc
.type
.r
= 1; // readable
249 initDesc
.dpl
= 0; // privilege
250 initDesc
.p
= 1; // present
251 initDesc
.l
= 1; // longmode - 64 bit
252 initDesc
.d
= 0; // operand size
253 initDesc
.s
= 1; // system segment
254 initDesc
.limit
= 0xFFFFFFFF;
257 //64 bit code segment
258 SegDescriptor csLowPLDesc
= initDesc
;
259 csLowPLDesc
.type
.codeOrData
= 1;
261 uint64_t csLowPLDescVal
= csLowPLDesc
;
262 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
263 (uint8_t *)(&csLowPLDescVal
), 8);
267 SegSelector csLowPL
= 0;
268 csLowPL
.si
= numGDTEntries
- 1;
271 //64 bit data segment
272 SegDescriptor dsLowPLDesc
= initDesc
;
273 dsLowPLDesc
.type
.codeOrData
= 0;
275 uint64_t dsLowPLDescVal
= dsLowPLDesc
;
276 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
277 (uint8_t *)(&dsLowPLDescVal
), 8);
281 SegSelector dsLowPL
= 0;
282 dsLowPL
.si
= numGDTEntries
- 1;
285 //64 bit data segment
286 SegDescriptor dsDesc
= initDesc
;
287 dsDesc
.type
.codeOrData
= 0;
289 uint64_t dsDescVal
= dsDesc
;
290 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
291 (uint8_t *)(&dsDescVal
), 8);
296 ds
.si
= numGDTEntries
- 1;
299 //64 bit code segment
300 SegDescriptor csDesc
= initDesc
;
301 csDesc
.type
.codeOrData
= 1;
303 uint64_t csDescVal
= csDesc
;
304 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
305 (uint8_t *)(&csDescVal
), 8);
310 cs
.si
= numGDTEntries
- 1;
313 SegSelector scall
= 0;
314 scall
.si
= csLowPL
.si
;
317 SegSelector sret
= 0;
318 sret
.si
= dsLowPL
.si
;
321 /* In long mode the TSS has been extended to 16 Bytes */
322 TSSlow TSSDescLow
= 0;
323 TSSDescLow
.type
= 0xB;
324 TSSDescLow
.dpl
= 0; // Privelege level 0
325 TSSDescLow
.p
= 1; // Present
326 TSSDescLow
.limit
= 0xFFFFFFFF;
327 TSSDescLow
.base
= bits(TSSVirtAddr
, 31, 0);
329 TSShigh TSSDescHigh
= 0;
330 TSSDescHigh
.base
= bits(TSSVirtAddr
, 63, 32);
335 } tssDescVal
= {TSSDescLow
, TSSDescHigh
};
337 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
338 (uint8_t *)(&tssDescVal
), sizeof(tssDescVal
));
342 SegSelector tssSel
= 0;
343 tssSel
.si
= numGDTEntries
- 1;
345 uint64_t tss_base_addr
= (TSSDescHigh
.base
<< 32) | TSSDescLow
.base
;
346 uint64_t tss_limit
= TSSDescLow
.limit
;
348 SegAttr tss_attr
= 0;
350 tss_attr
.type
= TSSDescLow
.type
;
351 tss_attr
.dpl
= TSSDescLow
.dpl
;
352 tss_attr
.present
= TSSDescLow
.p
;
353 tss_attr
.granularity
= TSSDescLow
.g
;
354 tss_attr
.unusable
= 0;
356 for (int i
= 0; i
< contextIds
.size(); i
++) {
357 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
359 tc
->setMiscReg(MISCREG_CS
, cs
);
360 tc
->setMiscReg(MISCREG_DS
, ds
);
361 tc
->setMiscReg(MISCREG_ES
, ds
);
362 tc
->setMiscReg(MISCREG_FS
, ds
);
363 tc
->setMiscReg(MISCREG_GS
, ds
);
364 tc
->setMiscReg(MISCREG_SS
, ds
);
367 tc
->setMiscReg(MISCREG_TSL
, 0);
371 tc
->setMiscReg(MISCREG_TSL_ATTR
, tslAttr
);
373 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
374 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 8 * numGDTEntries
- 1);
376 tc
->setMiscReg(MISCREG_TR
, tssSel
);
377 tc
->setMiscReg(MISCREG_TR_BASE
, tss_base_addr
);
378 tc
->setMiscReg(MISCREG_TR_EFF_BASE
, 0);
379 tc
->setMiscReg(MISCREG_TR_LIMIT
, tss_limit
);
380 tc
->setMiscReg(MISCREG_TR_ATTR
, tss_attr
);
382 //Start using longmode segments.
383 installSegDesc(tc
, SEGMENT_REG_CS
, csDesc
, true);
384 installSegDesc(tc
, SEGMENT_REG_DS
, dsDesc
, true);
385 installSegDesc(tc
, SEGMENT_REG_ES
, dsDesc
, true);
386 installSegDesc(tc
, SEGMENT_REG_FS
, dsDesc
, true);
387 installSegDesc(tc
, SEGMENT_REG_GS
, dsDesc
, true);
388 installSegDesc(tc
, SEGMENT_REG_SS
, dsDesc
, true);
391 efer
.sce
= 1; // Enable system call extensions.
392 efer
.lme
= 1; // Enable long mode.
393 efer
.lma
= 1; // Activate long mode.
394 efer
.nxe
= 0; // Enable nx support.
395 efer
.svme
= 1; // Enable svm support for now.
396 efer
.ffxsr
= 0; // Turn on fast fxsave and fxrstor.
397 tc
->setMiscReg(MISCREG_EFER
, efer
);
399 //Set up the registers that describe the operating mode.
401 cr0
.pg
= 1; // Turn on paging.
402 cr0
.cd
= 0; // Don't disable caching.
403 cr0
.nw
= 0; // This is bit is defined to be ignored.
404 cr0
.am
= 1; // No alignment checking
405 cr0
.wp
= 1; // Supervisor mode can write read only pages
407 cr0
.et
= 1; // This should always be 1
408 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
409 // would be pointless.
410 cr0
.em
= 0; // Allow x87 instructions to execute natively.
411 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
412 // setting it to one.
413 cr0
.pe
= 1; // We're definitely in protected mode.
414 tc
->setMiscReg(MISCREG_CR0
, cr0
);
417 tc
->setMiscReg(MISCREG_CR2
, cr2
);
419 CR3 cr3
= dynamic_cast<ArchPageTable
*>(pTable
)->basePtr();
420 tc
->setMiscReg(MISCREG_CR3
, cr3
);
424 cr4
.osxsave
= 1; // Enable XSAVE and Proc Extended States
425 cr4
.osxmmexcpt
= 1; // Operating System Unmasked Exception
426 cr4
.osfxsr
= 1; // Operating System FXSave/FSRSTOR Support
427 cr4
.pce
= 0; // Performance-Monitoring Counter Enable
428 cr4
.pge
= 0; // Page-Global Enable
429 cr4
.mce
= 0; // Machine Check Enable
430 cr4
.pae
= 1; // Physical-Address Extension
431 cr4
.pse
= 0; // Page Size Extensions
432 cr4
.de
= 0; // Debugging Extensions
433 cr4
.tsd
= 0; // Time Stamp Disable
434 cr4
.pvi
= 0; // Protected-Mode Virtual Interrupts
435 cr4
.vme
= 0; // Virtual-8086 Mode Extensions
437 tc
->setMiscReg(MISCREG_CR4
, cr4
);
440 tc
->setMiscReg(MISCREG_CR8
, cr8
);
442 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
444 tc
->setMiscReg(MISCREG_APIC_BASE
, 0xfee00900);
446 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
447 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 0xffff);
449 tc
->setMiscReg(MISCREG_IDTR_BASE
, IDTVirtAddr
);
450 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
452 /* enabling syscall and sysret */
453 RegVal star
= ((RegVal
)sret
<< 48) | ((RegVal
)scall
<< 32);
454 tc
->setMiscReg(MISCREG_STAR
, star
);
455 RegVal lstar
= (RegVal
)syscallCodeVirtAddr
;
456 tc
->setMiscReg(MISCREG_LSTAR
, lstar
);
457 RegVal sfmask
= (1 << 8) | (1 << 10); // TF | DF
458 tc
->setMiscReg(MISCREG_SF_MASK
, sfmask
);
461 /* Set up the content of the TSS and write it to physical memory. */
464 uint32_t reserved0
; // +00h
465 uint32_t RSP0_low
; // +04h
466 uint32_t RSP0_high
; // +08h
467 uint32_t RSP1_low
; // +0Ch
468 uint32_t RSP1_high
; // +10h
469 uint32_t RSP2_low
; // +14h
470 uint32_t RSP2_high
; // +18h
471 uint32_t reserved1
; // +1Ch
472 uint32_t reserved2
; // +20h
473 uint32_t IST1_low
; // +24h
474 uint32_t IST1_high
; // +28h
475 uint32_t IST2_low
; // +2Ch
476 uint32_t IST2_high
; // +30h
477 uint32_t IST3_low
; // +34h
478 uint32_t IST3_high
; // +38h
479 uint32_t IST4_low
; // +3Ch
480 uint32_t IST4_high
; // +40h
481 uint32_t IST5_low
; // +44h
482 uint32_t IST5_high
; // +48h
483 uint32_t IST6_low
; // +4Ch
484 uint32_t IST6_high
; // +50h
485 uint32_t IST7_low
; // +54h
486 uint32_t IST7_high
; // +58h
487 uint32_t reserved3
; // +5Ch
488 uint32_t reserved4
; // +60h
489 uint16_t reserved5
; // +64h
490 uint16_t IO_MapBase
; // +66h
493 /** setting Interrupt Stack Table */
494 uint64_t IST_start
= ISTVirtAddr
+ PageBytes
;
495 tss
.IST1_low
= IST_start
;
496 tss
.IST1_high
= IST_start
>> 32;
497 tss
.RSP0_low
= tss
.IST1_low
;
498 tss
.RSP0_high
= tss
.IST1_high
;
499 tss
.RSP1_low
= tss
.IST1_low
;
500 tss
.RSP1_high
= tss
.IST1_high
;
501 tss
.RSP2_low
= tss
.IST1_low
;
502 tss
.RSP2_high
= tss
.IST1_high
;
503 physProxy
.writeBlob(tssPhysAddr
, (uint8_t *)(&tss
), sizeof(tss
));
505 /* Setting IDT gates */
506 GateDescriptorLow PFGateLow
= 0;
507 PFGateLow
.offsetHigh
= bits(PFHandlerVirtAddr
, 31, 16);
508 PFGateLow
.offsetLow
= bits(PFHandlerVirtAddr
, 15, 0);
509 PFGateLow
.selector
= csLowPL
;
512 PFGateLow
.type
= 0xe; // gate interrupt type
513 PFGateLow
.IST
= 0; // setting IST to 0 and using RSP0
515 GateDescriptorHigh PFGateHigh
= 0;
516 PFGateHigh
.offset
= bits(PFHandlerVirtAddr
, 63, 32);
521 } PFGate
= {PFGateLow
, PFGateHigh
};
523 physProxy
.writeBlob(idtPhysAddr
+ 0xE0,
524 (uint8_t *)(&PFGate
), sizeof(PFGate
));
526 /* System call handler */
527 uint8_t syscallBlob
[] = {
528 // mov %rax, (0xffffc90000005600)
529 0x48, 0xa3, 0x00, 0x60, 0x00,
530 0x00, 0x00, 0xc9, 0xff, 0xff,
535 physProxy
.writeBlob(syscallCodePhysAddr
,
536 syscallBlob
, sizeof(syscallBlob
));
538 /** Page fault handler */
539 uint8_t faultBlob
[] = {
540 // mov %rax, (0xffffc90000005700)
541 0x48, 0xa3, 0x00, 0x61, 0x00,
542 0x00, 0x00, 0xc9, 0xff, 0xff,
543 // add $0x8, %rsp # skip error
544 0x48, 0x83, 0xc4, 0x08,
549 physProxy
.writeBlob(pfHandlerPhysAddr
, faultBlob
, sizeof(faultBlob
));
551 /* Syscall handler */
552 pTable
->map(syscallCodeVirtAddr
, syscallCodePhysAddr
,
555 pTable
->map(GDTVirtAddr
, gdtPhysAddr
, PageBytes
, false);
557 pTable
->map(IDTVirtAddr
, idtPhysAddr
, PageBytes
, false);
559 pTable
->map(TSSVirtAddr
, tssPhysAddr
, PageBytes
, false);
561 pTable
->map(ISTVirtAddr
, istPhysAddr
, PageBytes
, false);
563 pTable
->map(PFHandlerVirtAddr
, pfHandlerPhysAddr
, PageBytes
, false);
564 /* MMIO region for m5ops */
565 pTable
->map(MMIORegionVirtAddr
, MMIORegionPhysAddr
,
566 16 * PageBytes
, false);
568 for (int i
= 0; i
< contextIds
.size(); i
++) {
569 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
571 SegAttr dataAttr
= 0;
573 dataAttr
.unusable
= 0;
574 dataAttr
.defaultSize
= 1;
575 dataAttr
.longMode
= 1;
577 dataAttr
.granularity
= 1;
578 dataAttr
.present
= 1;
580 dataAttr
.writable
= 1;
581 dataAttr
.readable
= 1;
582 dataAttr
.expandDown
= 0;
585 // Initialize the segment registers.
586 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
587 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
588 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
589 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
595 csAttr
.defaultSize
= 0;
598 csAttr
.granularity
= 1;
603 csAttr
.expandDown
= 0;
606 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
609 efer
.sce
= 1; // Enable system call extensions.
610 efer
.lme
= 1; // Enable long mode.
611 efer
.lma
= 1; // Activate long mode.
612 efer
.nxe
= 1; // Enable nx support.
613 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
614 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
615 tc
->setMiscReg(MISCREG_EFER
, efer
);
617 // Set up the registers that describe the operating mode.
619 cr0
.pg
= 1; // Turn on paging.
620 cr0
.cd
= 0; // Don't disable caching.
621 cr0
.nw
= 0; // This is bit is defined to be ignored.
622 cr0
.am
= 0; // No alignment checking
623 cr0
.wp
= 0; // Supervisor mode can write read only pages
625 cr0
.et
= 1; // This should always be 1
626 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
627 // would be pointless.
628 cr0
.em
= 0; // Allow x87 instructions to execute natively.
629 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
630 // setting it to one.
631 cr0
.pe
= 1; // We're definitely in protected mode.
632 tc
->setMiscReg(MISCREG_CR0
, cr0
);
634 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
640 I386Process::initState()
642 X86Process::initState();
647 * Set up a GDT for this process. The whole GDT wouldn't really be for
648 * this process, but the only parts we care about are.
650 allocateMem(_gdtStart
, _gdtSize
);
652 assert(_gdtSize
% sizeof(zero
) == 0);
653 for (Addr gdtCurrent
= _gdtStart
;
654 gdtCurrent
< _gdtStart
+ _gdtSize
; gdtCurrent
+= sizeof(zero
)) {
655 initVirtMem
.write(gdtCurrent
, zero
);
658 // Set up the vsyscall page for this process.
659 allocateMem(vsyscallPage
.base
, vsyscallPage
.size
);
660 uint8_t vsyscallBlob
[] = {
664 0x89, 0xe5, // mov %esp, %ebp
665 0x0f, 0x34 // sysenter
667 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
,
668 vsyscallBlob
, sizeof(vsyscallBlob
));
670 uint8_t vsysexitBlob
[] = {
676 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsysexitOffset
,
677 vsysexitBlob
, sizeof(vsysexitBlob
));
679 for (int i
= 0; i
< contextIds
.size(); i
++) {
680 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
682 SegAttr dataAttr
= 0;
684 dataAttr
.unusable
= 0;
685 dataAttr
.defaultSize
= 1;
686 dataAttr
.longMode
= 0;
688 dataAttr
.granularity
= 1;
689 dataAttr
.present
= 1;
691 dataAttr
.writable
= 1;
692 dataAttr
.readable
= 1;
693 dataAttr
.expandDown
= 0;
696 // Initialize the segment registers.
697 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
698 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
699 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
700 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
701 tc
->setMiscRegNoEffect(MISCREG_SEG_SEL(seg
), 0xB);
702 tc
->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg
), (uint32_t)(-1));
708 csAttr
.defaultSize
= 1;
711 csAttr
.granularity
= 1;
716 csAttr
.expandDown
= 0;
719 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
721 tc
->setMiscRegNoEffect(MISCREG_TSG_BASE
, _gdtStart
);
722 tc
->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE
, _gdtStart
);
723 tc
->setMiscRegNoEffect(MISCREG_TSG_LIMIT
, _gdtStart
+ _gdtSize
- 1);
725 // Set the LDT selector to 0 to deactivate it.
726 tc
->setMiscRegNoEffect(MISCREG_TSL
, 0);
729 efer
.sce
= 1; // Enable system call extensions.
730 efer
.lme
= 1; // Enable long mode.
731 efer
.lma
= 0; // Deactivate long mode.
732 efer
.nxe
= 1; // Enable nx support.
733 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
734 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
735 tc
->setMiscReg(MISCREG_EFER
, efer
);
737 // Set up the registers that describe the operating mode.
739 cr0
.pg
= 1; // Turn on paging.
740 cr0
.cd
= 0; // Don't disable caching.
741 cr0
.nw
= 0; // This is bit is defined to be ignored.
742 cr0
.am
= 0; // No alignment checking
743 cr0
.wp
= 0; // Supervisor mode can write read only pages
745 cr0
.et
= 1; // This should always be 1
746 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
747 // would be pointless.
748 cr0
.em
= 0; // Allow x87 instructions to execute natively.
749 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
750 // setting it to one.
751 cr0
.pe
= 1; // We're definitely in protected mode.
752 tc
->setMiscReg(MISCREG_CR0
, cr0
);
754 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
758 template<class IntType
>
760 X86Process::argsInit(int pageSize
,
761 std::vector
<AuxVector
<IntType
> > extraAuxvs
)
763 int intSize
= sizeof(IntType
);
765 std::vector
<AuxVector
<IntType
>> auxv
= extraAuxvs
;
773 // We want 16 byte alignment
776 // Patch the ld_bias for dynamic executables.
779 // load object file into target memory
780 objFile
->loadSections(initVirtMem
);
783 X86_OnboardFPU
= 1 << 0,
784 X86_VirtualModeExtensions
= 1 << 1,
785 X86_DebuggingExtensions
= 1 << 2,
786 X86_PageSizeExtensions
= 1 << 3,
788 X86_TimeStampCounter
= 1 << 4,
789 X86_ModelSpecificRegisters
= 1 << 5,
790 X86_PhysicalAddressExtensions
= 1 << 6,
791 X86_MachineCheckExtensions
= 1 << 7,
793 X86_CMPXCHG8Instruction
= 1 << 8,
794 X86_OnboardAPIC
= 1 << 9,
795 X86_SYSENTER_SYSEXIT
= 1 << 11,
797 X86_MemoryTypeRangeRegisters
= 1 << 12,
798 X86_PageGlobalEnable
= 1 << 13,
799 X86_MachineCheckArchitecture
= 1 << 14,
800 X86_CMOVInstruction
= 1 << 15,
802 X86_PageAttributeTable
= 1 << 16,
803 X86_36BitPSEs
= 1 << 17,
804 X86_ProcessorSerialNumber
= 1 << 18,
805 X86_CLFLUSHInstruction
= 1 << 19,
807 X86_DebugTraceStore
= 1 << 21,
808 X86_ACPIViaMSR
= 1 << 22,
809 X86_MultimediaExtensions
= 1 << 23,
811 X86_FXSAVE_FXRSTOR
= 1 << 24,
812 X86_StreamingSIMDExtensions
= 1 << 25,
813 X86_StreamingSIMDExtensions2
= 1 << 26,
814 X86_CPUSelfSnoop
= 1 << 27,
816 X86_HyperThreading
= 1 << 28,
817 X86_AutomaticClockControl
= 1 << 29,
818 X86_IA64Processor
= 1 << 30
821 // Setup the auxiliary vectors. These will already have endian
822 // conversion. Auxiliary vectors are loaded only for elf formatted
823 // executables; the auxv is responsible for passing information from
824 // the OS to the interpreter.
825 ElfObject
* elfObject
= dynamic_cast<ElfObject
*>(objFile
);
829 X86_VirtualModeExtensions
|
830 X86_DebuggingExtensions
|
831 X86_PageSizeExtensions
|
832 X86_TimeStampCounter
|
833 X86_ModelSpecificRegisters
|
834 X86_PhysicalAddressExtensions
|
835 X86_MachineCheckExtensions
|
836 X86_CMPXCHG8Instruction
|
838 X86_SYSENTER_SYSEXIT
|
839 X86_MemoryTypeRangeRegisters
|
840 X86_PageGlobalEnable
|
841 X86_MachineCheckArchitecture
|
842 X86_CMOVInstruction
|
843 X86_PageAttributeTable
|
845 // X86_ProcessorSerialNumber |
846 X86_CLFLUSHInstruction
|
847 // X86_DebugTraceStore |
849 X86_MultimediaExtensions
|
851 X86_StreamingSIMDExtensions
|
852 X86_StreamingSIMDExtensions2
|
853 // X86_CPUSelfSnoop |
854 // X86_HyperThreading |
855 // X86_AutomaticClockControl |
856 // X86_IA64Processor |
859 // Bits which describe the system hardware capabilities
860 // XXX Figure out what these should be
861 auxv
.emplace_back(M5_AT_HWCAP
, features
);
862 // The system page size
863 auxv
.emplace_back(M5_AT_PAGESZ
, X86ISA::PageBytes
);
864 // Frequency at which times() increments
865 // Defined to be 100 in the kernel source.
866 auxv
.emplace_back(M5_AT_CLKTCK
, 100);
867 // This is the virtual address of the program header tables if they
868 // appear in the executable image.
869 auxv
.emplace_back(M5_AT_PHDR
, elfObject
->programHeaderTable());
870 // This is the size of a program header entry from the elf file.
871 auxv
.emplace_back(M5_AT_PHENT
, elfObject
->programHeaderSize());
872 // This is the number of program headers from the original elf file.
873 auxv
.emplace_back(M5_AT_PHNUM
, elfObject
->programHeaderCount());
874 // This is the base address of the ELF interpreter; it should be
875 // zero for static executables or contain the base address for
876 // dynamic executables.
877 auxv
.emplace_back(M5_AT_BASE
, getBias());
878 // XXX Figure out what this should be.
879 auxv
.emplace_back(M5_AT_FLAGS
, 0);
880 // The entry point to the program
881 auxv
.emplace_back(M5_AT_ENTRY
, objFile
->entryPoint());
882 // Different user and group IDs
883 auxv
.emplace_back(M5_AT_UID
, uid());
884 auxv
.emplace_back(M5_AT_EUID
, euid());
885 auxv
.emplace_back(M5_AT_GID
, gid());
886 auxv
.emplace_back(M5_AT_EGID
, egid());
887 // Whether to enable "secure mode" in the executable
888 auxv
.emplace_back(M5_AT_SECURE
, 0);
889 // The address of 16 "random" bytes.
890 auxv
.emplace_back(M5_AT_RANDOM
, 0);
891 // The name of the program
892 auxv
.emplace_back(M5_AT_EXECFN
, 0);
893 // The platform string
894 auxv
.emplace_back(M5_AT_PLATFORM
, 0);
897 // Figure out how big the initial stack needs to be
899 // A sentry NULL void pointer at the top of the stack.
900 int sentry_size
= intSize
;
902 // This is the name of the file which is present on the initial stack
903 // It's purpose is to let the user space linker examine the original file.
904 int file_name_size
= filename
.size() + 1;
906 const int numRandomBytes
= 16;
907 int aux_data_size
= numRandomBytes
;
909 string platform
= "x86_64";
910 aux_data_size
+= platform
.size() + 1;
912 int env_data_size
= 0;
913 for (int i
= 0; i
< envp
.size(); ++i
)
914 env_data_size
+= envp
[i
].size() + 1;
915 int arg_data_size
= 0;
916 for (int i
= 0; i
< argv
.size(); ++i
)
917 arg_data_size
+= argv
[i
].size() + 1;
919 // The info_block needs to be padded so its size is a multiple of the
920 // alignment mask. Also, it appears that there needs to be at least some
921 // padding, so if the size is already a multiple, we need to increase it
923 int base_info_block_size
=
924 sentry_size
+ file_name_size
+ env_data_size
+ arg_data_size
;
926 int info_block_size
= roundUp(base_info_block_size
, align
);
928 int info_block_padding
= info_block_size
- base_info_block_size
;
930 // Each auxiliary vector is two 8 byte words
931 int aux_array_size
= intSize
* 2 * (auxv
.size() + 1);
933 int envp_array_size
= intSize
* (envp
.size() + 1);
934 int argv_array_size
= intSize
* (argv
.size() + 1);
936 int argc_size
= intSize
;
938 // Figure out the size of the contents of the actual initial frame
945 // There needs to be padding after the auxiliary vector data so that the
946 // very bottom of the stack is aligned properly.
947 int partial_size
= frame_size
+ aux_data_size
;
948 int aligned_partial_size
= roundUp(partial_size
, align
);
949 int aux_padding
= aligned_partial_size
- partial_size
;
957 Addr stack_base
= memState
->getStackBase();
959 Addr stack_min
= stack_base
- space_needed
;
960 stack_min
= roundDown(stack_min
, align
);
962 unsigned stack_size
= stack_base
- stack_min
;
963 stack_size
= roundUp(stack_size
, pageSize
);
964 memState
->setStackSize(stack_size
);
967 Addr stack_end
= roundDown(stack_base
- stack_size
, pageSize
);
969 DPRINTF(Stack
, "Mapping the stack: 0x%x %dB\n", stack_end
, stack_size
);
970 allocateMem(stack_end
, stack_size
);
972 // map out initial stack contents
973 IntType sentry_base
= stack_base
- sentry_size
;
974 IntType file_name_base
= sentry_base
- file_name_size
;
975 IntType env_data_base
= file_name_base
- env_data_size
;
976 IntType arg_data_base
= env_data_base
- arg_data_size
;
977 IntType aux_data_base
= arg_data_base
- info_block_padding
- aux_data_size
;
978 IntType auxv_array_base
= aux_data_base
- aux_array_size
- aux_padding
;
979 IntType envp_array_base
= auxv_array_base
- envp_array_size
;
980 IntType argv_array_base
= envp_array_base
- argv_array_size
;
981 IntType argc_base
= argv_array_base
- argc_size
;
983 DPRINTF(Stack
, "The addresses of items on the initial stack:\n");
984 DPRINTF(Stack
, "0x%x - file name\n", file_name_base
);
985 DPRINTF(Stack
, "0x%x - env data\n", env_data_base
);
986 DPRINTF(Stack
, "0x%x - arg data\n", arg_data_base
);
987 DPRINTF(Stack
, "0x%x - aux data\n", aux_data_base
);
988 DPRINTF(Stack
, "0x%x - auxv array\n", auxv_array_base
);
989 DPRINTF(Stack
, "0x%x - envp array\n", envp_array_base
);
990 DPRINTF(Stack
, "0x%x - argv array\n", argv_array_base
);
991 DPRINTF(Stack
, "0x%x - argc \n", argc_base
);
992 DPRINTF(Stack
, "0x%x - stack min\n", stack_min
);
994 // write contents to stack
997 IntType argc
= argv
.size();
998 IntType guestArgc
= X86ISA::htog(argc
);
1000 // Write out the sentry void *
1001 IntType sentry_NULL
= 0;
1002 initVirtMem
.writeBlob(sentry_base
, (uint8_t*)&sentry_NULL
, sentry_size
);
1004 // Write the file name
1005 initVirtMem
.writeString(file_name_base
, filename
.c_str());
1007 // Fix up the aux vectors which point to data
1008 assert(auxv
[auxv
.size() - 3].type
== M5_AT_RANDOM
);
1009 auxv
[auxv
.size() - 3].val
= aux_data_base
;
1010 assert(auxv
[auxv
.size() - 2].type
== M5_AT_EXECFN
);
1011 auxv
[auxv
.size() - 2].val
= argv_array_base
;
1012 assert(auxv
[auxv
.size() - 1].type
== M5_AT_PLATFORM
);
1013 auxv
[auxv
.size() - 1].val
= aux_data_base
+ numRandomBytes
;
1016 // Copy the aux stuff
1017 Addr auxv_array_end
= auxv_array_base
;
1018 for (const auto &aux
: auxv
) {
1019 initVirtMem
.write(auxv_array_end
, aux
, GuestByteOrder
);
1020 auxv_array_end
+= sizeof(aux
);
1022 // Write out the terminating zeroed auxiliary vector
1023 const AuxVector
<uint64_t> zero(0, 0);
1024 initVirtMem
.write(auxv_array_end
, zero
);
1025 auxv_array_end
+= sizeof(zero
);
1027 initVirtMem
.writeString(aux_data_base
, platform
.c_str());
1029 copyStringArray(envp
, envp_array_base
, env_data_base
, initVirtMem
);
1030 copyStringArray(argv
, argv_array_base
, arg_data_base
, initVirtMem
);
1032 initVirtMem
.writeBlob(argc_base
, (uint8_t*)&guestArgc
, intSize
);
1034 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
1035 // Set the stack pointer register
1036 tc
->setIntReg(StackPointerReg
, stack_min
);
1038 // There doesn't need to be any segment base added in since we're dealing
1039 // with the flat segmentation model.
1040 tc
->pcState(getStartPC());
1042 // Align the "stack_min" to a page boundary.
1043 memState
->setStackMin(roundDown(stack_min
, pageSize
));
1047 X86_64Process::argsInit(int pageSize
)
1049 std::vector
<AuxVector
<uint64_t> > extraAuxvs
;
1050 extraAuxvs
.emplace_back(M5_AT_SYSINFO_EHDR
, vsyscallPage
.base
);
1051 X86Process::argsInit
<uint64_t>(pageSize
, extraAuxvs
);
1055 I386Process::argsInit(int pageSize
)
1057 std::vector
<AuxVector
<uint32_t> > extraAuxvs
;
1058 //Tell the binary where the vsyscall part of the vsyscall page is.
1059 extraAuxvs
.emplace_back(M5_AT_SYSINFO
,
1060 vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
);
1061 extraAuxvs
.emplace_back(M5_AT_SYSINFO_EHDR
, vsyscallPage
.base
);
1062 X86Process::argsInit
<uint32_t>(pageSize
, extraAuxvs
);
1066 X86Process::setSyscallReturn(ThreadContext
*tc
, SyscallReturn retval
)
1068 tc
->setIntReg(INTREG_RAX
, retval
.encodedValue());
1072 X86_64Process::getSyscallArg(ThreadContext
*tc
, int &i
)
1074 assert(i
< NumArgumentRegs
);
1075 return tc
->readIntReg(ArgumentReg
[i
++]);
1079 X86_64Process::setSyscallArg(ThreadContext
*tc
, int i
, RegVal val
)
1081 assert(i
< NumArgumentRegs
);
1082 return tc
->setIntReg(ArgumentReg
[i
], val
);
1086 X86_64Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1087 Process
*p
, RegVal flags
)
1089 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1090 ((X86_64Process
*)p
)->vsyscallPage
= vsyscallPage
;
1094 I386Process::getSyscallArg(ThreadContext
*tc
, int &i
)
1096 assert(i
< NumArgumentRegs32
);
1097 return tc
->readIntReg(ArgumentReg32
[i
++]);
1101 I386Process::getSyscallArg(ThreadContext
*tc
, int &i
, int width
)
1103 assert(width
== 32 || width
== 64);
1104 assert(i
< NumArgumentRegs
);
1105 uint64_t retVal
= tc
->readIntReg(ArgumentReg32
[i
++]) & mask(32);
1107 retVal
|= ((uint64_t)tc
->readIntReg(ArgumentReg
[i
++]) << 32);
1112 I386Process::setSyscallArg(ThreadContext
*tc
, int i
, RegVal val
)
1114 assert(i
< NumArgumentRegs
);
1115 return tc
->setIntReg(ArgumentReg
[i
], val
);
1119 I386Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1120 Process
*p
, RegVal flags
)
1122 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1123 ((I386Process
*)p
)->vsyscallPage
= vsyscallPage
;