2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 #include "arch/x86/process.hh"
50 #include "arch/x86/isa_traits.hh"
51 #include "arch/x86/regs/misc.hh"
52 #include "arch/x86/regs/segment.hh"
53 #include "arch/x86/system.hh"
54 #include "arch/x86/types.hh"
55 #include "base/loader/elf_object.hh"
56 #include "base/loader/object_file.hh"
57 #include "base/logging.hh"
58 #include "base/trace.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/Stack.hh"
61 #include "mem/multi_level_page_table.hh"
62 #include "mem/page_table.hh"
63 #include "params/Process.hh"
64 #include "sim/aux_vector.hh"
65 #include "sim/process_impl.hh"
66 #include "sim/syscall_desc.hh"
67 #include "sim/syscall_return.hh"
68 #include "sim/system.hh"
71 using namespace X86ISA
;
73 static const int ArgumentReg
[] = {
77 // This argument register is r10 for syscalls and rcx for C.
84 static const int NumArgumentRegs M5_VAR_USED
=
85 sizeof(ArgumentReg
) / sizeof(const int);
87 static const int ArgumentReg32
[] = {
96 static const int NumArgumentRegs32 M5_VAR_USED
=
97 sizeof(ArgumentReg
) / sizeof(const int);
99 template class MultiLevelPageTable
<LongModePTE
<47, 39>,
102 LongModePTE
<20, 12> >;
103 typedef MultiLevelPageTable
<LongModePTE
<47, 39>,
106 LongModePTE
<20, 12> > ArchPageTable
;
108 X86Process::X86Process(ProcessParams
*params
, ObjectFile
*objFile
,
109 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
110 : Process(params
, params
->useArchPT
?
111 static_cast<EmulationPageTable
*>(
112 new ArchPageTable(params
->name
, params
->pid
,
113 params
->system
, PageBytes
)) :
114 new EmulationPageTable(params
->name
, params
->pid
,
117 syscallDescs(_syscallDescs
), numSyscallDescs(_numSyscallDescs
)
121 void X86Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
122 Process
*p
, RegVal flags
)
124 Process::clone(old_tc
, new_tc
, p
, flags
);
125 X86Process
*process
= (X86Process
*)p
;
129 X86_64Process::X86_64Process(ProcessParams
*params
, ObjectFile
*objFile
,
130 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
131 : X86Process(params
, objFile
, _syscallDescs
, _numSyscallDescs
)
134 vsyscallPage
.base
= 0xffffffffff600000ULL
;
135 vsyscallPage
.size
= PageBytes
;
136 vsyscallPage
.vtimeOffset
= 0x400;
137 vsyscallPage
.vgettimeofdayOffset
= 0x0;
139 Addr brk_point
= roundUp(image
.maxAddr(), PageBytes
);
140 Addr stack_base
= 0x7FFFFFFFF000ULL
;
141 Addr max_stack_size
= 8 * 1024 * 1024;
142 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
143 Addr mmap_end
= 0x7FFFF7FFF000ULL
;
145 memState
= make_shared
<MemState
>(brk_point
, stack_base
, max_stack_size
,
146 next_thread_stack_base
, mmap_end
);
150 I386Process::syscall(int64_t callnum
, ThreadContext
*tc
, Fault
*fault
)
152 PCState pc
= tc
->pcState();
154 if (eip
>= vsyscallPage
.base
&&
155 eip
< vsyscallPage
.base
+ vsyscallPage
.size
) {
156 pc
.npc(vsyscallPage
.base
+ vsyscallPage
.vsysexitOffset
);
159 X86Process::syscall(callnum
, tc
, fault
);
163 I386Process::I386Process(ProcessParams
*params
, ObjectFile
*objFile
,
164 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
165 : X86Process(params
, objFile
, _syscallDescs
, _numSyscallDescs
)
168 panic("KVM CPU model does not support 32 bit processes");
170 _gdtStart
= ULL(0xffffd000);
171 _gdtSize
= PageBytes
;
173 vsyscallPage
.base
= 0xffffe000ULL
;
174 vsyscallPage
.size
= PageBytes
;
175 vsyscallPage
.vsyscallOffset
= 0x400;
176 vsyscallPage
.vsysexitOffset
= 0x410;
178 Addr brk_point
= roundUp(image
.maxAddr(), PageBytes
);
179 Addr stack_base
= _gdtStart
;
180 Addr max_stack_size
= 8 * 1024 * 1024;
181 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
182 Addr mmap_end
= 0xB7FFF000ULL
;
184 memState
= make_shared
<MemState
>(brk_point
, stack_base
, max_stack_size
,
185 next_thread_stack_base
, mmap_end
);
189 X86Process::getDesc(int callnum
)
191 if (callnum
< 0 || callnum
>= numSyscallDescs
)
193 return &syscallDescs
[callnum
];
197 X86_64Process::initState()
199 X86Process::initState();
206 // Set up the vsyscall page for this process.
207 allocateMem(vsyscallPage
.base
, vsyscallPage
.size
);
208 uint8_t vtimeBlob
[] = {
209 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
210 0x0f,0x05, // syscall
213 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vtimeOffset
,
214 vtimeBlob
, sizeof(vtimeBlob
));
216 uint8_t vgettimeofdayBlob
[] = {
217 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
218 0x0f,0x05, // syscall
221 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vgettimeofdayOffset
,
222 vgettimeofdayBlob
, sizeof(vgettimeofdayBlob
));
225 PortProxy physProxy
= system
->physProxy
;
227 Addr syscallCodePhysAddr
= system
->allocPhysPages(1);
228 Addr gdtPhysAddr
= system
->allocPhysPages(1);
229 Addr idtPhysAddr
= system
->allocPhysPages(1);
230 Addr istPhysAddr
= system
->allocPhysPages(1);
231 Addr tssPhysAddr
= system
->allocPhysPages(1);
232 Addr pfHandlerPhysAddr
= system
->allocPhysPages(1);
237 uint8_t numGDTEntries
= 0;
238 uint64_t nullDescriptor
= 0;
239 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
243 SegDescriptor initDesc
= 0;
244 initDesc
.type
.codeOrData
= 0; // code or data type
245 initDesc
.type
.c
= 0; // conforming
246 initDesc
.type
.r
= 1; // readable
247 initDesc
.dpl
= 0; // privilege
248 initDesc
.p
= 1; // present
249 initDesc
.l
= 1; // longmode - 64 bit
250 initDesc
.d
= 0; // operand size
251 initDesc
.s
= 1; // system segment
252 initDesc
.limit
= 0xFFFFFFFF;
255 //64 bit code segment
256 SegDescriptor csLowPLDesc
= initDesc
;
257 csLowPLDesc
.type
.codeOrData
= 1;
259 uint64_t csLowPLDescVal
= csLowPLDesc
;
260 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
265 SegSelector csLowPL
= 0;
266 csLowPL
.si
= numGDTEntries
- 1;
269 //64 bit data segment
270 SegDescriptor dsLowPLDesc
= initDesc
;
271 dsLowPLDesc
.type
.codeOrData
= 0;
273 uint64_t dsLowPLDescVal
= dsLowPLDesc
;
274 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
279 SegSelector dsLowPL
= 0;
280 dsLowPL
.si
= numGDTEntries
- 1;
283 //64 bit data segment
284 SegDescriptor dsDesc
= initDesc
;
285 dsDesc
.type
.codeOrData
= 0;
287 uint64_t dsDescVal
= dsDesc
;
288 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
294 ds
.si
= numGDTEntries
- 1;
297 //64 bit code segment
298 SegDescriptor csDesc
= initDesc
;
299 csDesc
.type
.codeOrData
= 1;
301 uint64_t csDescVal
= csDesc
;
302 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
308 cs
.si
= numGDTEntries
- 1;
311 SegSelector scall
= 0;
312 scall
.si
= csLowPL
.si
;
315 SegSelector sret
= 0;
316 sret
.si
= dsLowPL
.si
;
319 /* In long mode the TSS has been extended to 16 Bytes */
320 TSSlow TSSDescLow
= 0;
321 TSSDescLow
.type
= 0xB;
322 TSSDescLow
.dpl
= 0; // Privelege level 0
323 TSSDescLow
.p
= 1; // Present
324 TSSDescLow
.limit
= 0xFFFFFFFF;
325 TSSDescLow
.base
= bits(TSSVirtAddr
, 31, 0);
327 TSShigh TSSDescHigh
= 0;
328 TSSDescHigh
.base
= bits(TSSVirtAddr
, 63, 32);
333 } tssDescVal
= {TSSDescLow
, TSSDescHigh
};
335 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
336 &tssDescVal
, sizeof(tssDescVal
));
340 SegSelector tssSel
= 0;
341 tssSel
.si
= numGDTEntries
- 1;
343 uint64_t tss_base_addr
= (TSSDescHigh
.base
<< 32) | TSSDescLow
.base
;
344 uint64_t tss_limit
= TSSDescLow
.limit
;
346 SegAttr tss_attr
= 0;
348 tss_attr
.type
= TSSDescLow
.type
;
349 tss_attr
.dpl
= TSSDescLow
.dpl
;
350 tss_attr
.present
= TSSDescLow
.p
;
351 tss_attr
.granularity
= TSSDescLow
.g
;
352 tss_attr
.unusable
= 0;
354 for (int i
= 0; i
< contextIds
.size(); i
++) {
355 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
357 tc
->setMiscReg(MISCREG_CS
, cs
);
358 tc
->setMiscReg(MISCREG_DS
, ds
);
359 tc
->setMiscReg(MISCREG_ES
, ds
);
360 tc
->setMiscReg(MISCREG_FS
, ds
);
361 tc
->setMiscReg(MISCREG_GS
, ds
);
362 tc
->setMiscReg(MISCREG_SS
, ds
);
365 tc
->setMiscReg(MISCREG_TSL
, 0);
369 tc
->setMiscReg(MISCREG_TSL_ATTR
, tslAttr
);
371 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
372 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 8 * numGDTEntries
- 1);
374 tc
->setMiscReg(MISCREG_TR
, tssSel
);
375 tc
->setMiscReg(MISCREG_TR_BASE
, tss_base_addr
);
376 tc
->setMiscReg(MISCREG_TR_EFF_BASE
, 0);
377 tc
->setMiscReg(MISCREG_TR_LIMIT
, tss_limit
);
378 tc
->setMiscReg(MISCREG_TR_ATTR
, tss_attr
);
380 //Start using longmode segments.
381 installSegDesc(tc
, SEGMENT_REG_CS
, csDesc
, true);
382 installSegDesc(tc
, SEGMENT_REG_DS
, dsDesc
, true);
383 installSegDesc(tc
, SEGMENT_REG_ES
, dsDesc
, true);
384 installSegDesc(tc
, SEGMENT_REG_FS
, dsDesc
, true);
385 installSegDesc(tc
, SEGMENT_REG_GS
, dsDesc
, true);
386 installSegDesc(tc
, SEGMENT_REG_SS
, dsDesc
, true);
389 efer
.sce
= 1; // Enable system call extensions.
390 efer
.lme
= 1; // Enable long mode.
391 efer
.lma
= 1; // Activate long mode.
392 efer
.nxe
= 0; // Enable nx support.
393 efer
.svme
= 1; // Enable svm support for now.
394 efer
.ffxsr
= 0; // Turn on fast fxsave and fxrstor.
395 tc
->setMiscReg(MISCREG_EFER
, efer
);
397 //Set up the registers that describe the operating mode.
399 cr0
.pg
= 1; // Turn on paging.
400 cr0
.cd
= 0; // Don't disable caching.
401 cr0
.nw
= 0; // This is bit is defined to be ignored.
402 cr0
.am
= 1; // No alignment checking
403 cr0
.wp
= 1; // Supervisor mode can write read only pages
405 cr0
.et
= 1; // This should always be 1
406 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
407 // would be pointless.
408 cr0
.em
= 0; // Allow x87 instructions to execute natively.
409 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
410 // setting it to one.
411 cr0
.pe
= 1; // We're definitely in protected mode.
412 tc
->setMiscReg(MISCREG_CR0
, cr0
);
415 tc
->setMiscReg(MISCREG_CR2
, cr2
);
417 CR3 cr3
= dynamic_cast<ArchPageTable
*>(pTable
)->basePtr();
418 tc
->setMiscReg(MISCREG_CR3
, cr3
);
422 cr4
.osxsave
= 1; // Enable XSAVE and Proc Extended States
423 cr4
.osxmmexcpt
= 1; // Operating System Unmasked Exception
424 cr4
.osfxsr
= 1; // Operating System FXSave/FSRSTOR Support
425 cr4
.pce
= 0; // Performance-Monitoring Counter Enable
426 cr4
.pge
= 0; // Page-Global Enable
427 cr4
.mce
= 0; // Machine Check Enable
428 cr4
.pae
= 1; // Physical-Address Extension
429 cr4
.pse
= 0; // Page Size Extensions
430 cr4
.de
= 0; // Debugging Extensions
431 cr4
.tsd
= 0; // Time Stamp Disable
432 cr4
.pvi
= 0; // Protected-Mode Virtual Interrupts
433 cr4
.vme
= 0; // Virtual-8086 Mode Extensions
435 tc
->setMiscReg(MISCREG_CR4
, cr4
);
438 tc
->setMiscReg(MISCREG_CR8
, cr8
);
440 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
442 tc
->setMiscReg(MISCREG_APIC_BASE
, 0xfee00900);
444 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
445 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 0xffff);
447 tc
->setMiscReg(MISCREG_IDTR_BASE
, IDTVirtAddr
);
448 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
450 /* enabling syscall and sysret */
451 RegVal star
= ((RegVal
)sret
<< 48) | ((RegVal
)scall
<< 32);
452 tc
->setMiscReg(MISCREG_STAR
, star
);
453 RegVal lstar
= (RegVal
)syscallCodeVirtAddr
;
454 tc
->setMiscReg(MISCREG_LSTAR
, lstar
);
455 RegVal sfmask
= (1 << 8) | (1 << 10); // TF | DF
456 tc
->setMiscReg(MISCREG_SF_MASK
, sfmask
);
459 /* Set up the content of the TSS and write it to physical memory. */
462 uint32_t reserved0
; // +00h
463 uint32_t RSP0_low
; // +04h
464 uint32_t RSP0_high
; // +08h
465 uint32_t RSP1_low
; // +0Ch
466 uint32_t RSP1_high
; // +10h
467 uint32_t RSP2_low
; // +14h
468 uint32_t RSP2_high
; // +18h
469 uint32_t reserved1
; // +1Ch
470 uint32_t reserved2
; // +20h
471 uint32_t IST1_low
; // +24h
472 uint32_t IST1_high
; // +28h
473 uint32_t IST2_low
; // +2Ch
474 uint32_t IST2_high
; // +30h
475 uint32_t IST3_low
; // +34h
476 uint32_t IST3_high
; // +38h
477 uint32_t IST4_low
; // +3Ch
478 uint32_t IST4_high
; // +40h
479 uint32_t IST5_low
; // +44h
480 uint32_t IST5_high
; // +48h
481 uint32_t IST6_low
; // +4Ch
482 uint32_t IST6_high
; // +50h
483 uint32_t IST7_low
; // +54h
484 uint32_t IST7_high
; // +58h
485 uint32_t reserved3
; // +5Ch
486 uint32_t reserved4
; // +60h
487 uint16_t reserved5
; // +64h
488 uint16_t IO_MapBase
; // +66h
491 /** setting Interrupt Stack Table */
492 uint64_t IST_start
= ISTVirtAddr
+ PageBytes
;
493 tss
.IST1_low
= IST_start
;
494 tss
.IST1_high
= IST_start
>> 32;
495 tss
.RSP0_low
= tss
.IST1_low
;
496 tss
.RSP0_high
= tss
.IST1_high
;
497 tss
.RSP1_low
= tss
.IST1_low
;
498 tss
.RSP1_high
= tss
.IST1_high
;
499 tss
.RSP2_low
= tss
.IST1_low
;
500 tss
.RSP2_high
= tss
.IST1_high
;
501 physProxy
.writeBlob(tssPhysAddr
, &tss
, sizeof(tss
));
503 /* Setting IDT gates */
504 GateDescriptorLow PFGateLow
= 0;
505 PFGateLow
.offsetHigh
= bits(PFHandlerVirtAddr
, 31, 16);
506 PFGateLow
.offsetLow
= bits(PFHandlerVirtAddr
, 15, 0);
507 PFGateLow
.selector
= csLowPL
;
510 PFGateLow
.type
= 0xe; // gate interrupt type
511 PFGateLow
.IST
= 0; // setting IST to 0 and using RSP0
513 GateDescriptorHigh PFGateHigh
= 0;
514 PFGateHigh
.offset
= bits(PFHandlerVirtAddr
, 63, 32);
519 } PFGate
= {PFGateLow
, PFGateHigh
};
521 physProxy
.writeBlob(idtPhysAddr
+ 0xE0, &PFGate
, sizeof(PFGate
));
523 /* System call handler */
524 uint8_t syscallBlob
[] = {
525 // mov %rax, (0xffffc90000005600)
526 0x48, 0xa3, 0x00, 0x60, 0x00,
527 0x00, 0x00, 0xc9, 0xff, 0xff,
532 physProxy
.writeBlob(syscallCodePhysAddr
,
533 syscallBlob
, sizeof(syscallBlob
));
535 /** Page fault handler */
536 uint8_t faultBlob
[] = {
537 // mov %rax, (0xffffc90000005700)
538 0x48, 0xa3, 0x00, 0x61, 0x00,
539 0x00, 0x00, 0xc9, 0xff, 0xff,
540 // add $0x8, %rsp # skip error
541 0x48, 0x83, 0xc4, 0x08,
546 physProxy
.writeBlob(pfHandlerPhysAddr
, faultBlob
, sizeof(faultBlob
));
548 /* Syscall handler */
549 pTable
->map(syscallCodeVirtAddr
, syscallCodePhysAddr
,
552 pTable
->map(GDTVirtAddr
, gdtPhysAddr
, PageBytes
, false);
554 pTable
->map(IDTVirtAddr
, idtPhysAddr
, PageBytes
, false);
556 pTable
->map(TSSVirtAddr
, tssPhysAddr
, PageBytes
, false);
558 pTable
->map(ISTVirtAddr
, istPhysAddr
, PageBytes
, false);
560 pTable
->map(PFHandlerVirtAddr
, pfHandlerPhysAddr
, PageBytes
, false);
561 /* MMIO region for m5ops */
562 pTable
->map(MMIORegionVirtAddr
, MMIORegionPhysAddr
,
563 16 * PageBytes
, false);
565 for (int i
= 0; i
< contextIds
.size(); i
++) {
566 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
568 SegAttr dataAttr
= 0;
570 dataAttr
.unusable
= 0;
571 dataAttr
.defaultSize
= 1;
572 dataAttr
.longMode
= 1;
574 dataAttr
.granularity
= 1;
575 dataAttr
.present
= 1;
577 dataAttr
.writable
= 1;
578 dataAttr
.readable
= 1;
579 dataAttr
.expandDown
= 0;
582 // Initialize the segment registers.
583 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
584 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
585 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
586 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
592 csAttr
.defaultSize
= 0;
595 csAttr
.granularity
= 1;
600 csAttr
.expandDown
= 0;
603 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
606 efer
.sce
= 1; // Enable system call extensions.
607 efer
.lme
= 1; // Enable long mode.
608 efer
.lma
= 1; // Activate long mode.
609 efer
.nxe
= 1; // Enable nx support.
610 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
611 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
612 tc
->setMiscReg(MISCREG_EFER
, efer
);
614 // Set up the registers that describe the operating mode.
616 cr0
.pg
= 1; // Turn on paging.
617 cr0
.cd
= 0; // Don't disable caching.
618 cr0
.nw
= 0; // This is bit is defined to be ignored.
619 cr0
.am
= 0; // No alignment checking
620 cr0
.wp
= 0; // Supervisor mode can write read only pages
622 cr0
.et
= 1; // This should always be 1
623 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
624 // would be pointless.
625 cr0
.em
= 0; // Allow x87 instructions to execute natively.
626 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
627 // setting it to one.
628 cr0
.pe
= 1; // We're definitely in protected mode.
629 tc
->setMiscReg(MISCREG_CR0
, cr0
);
631 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
637 I386Process::initState()
639 X86Process::initState();
644 * Set up a GDT for this process. The whole GDT wouldn't really be for
645 * this process, but the only parts we care about are.
647 allocateMem(_gdtStart
, _gdtSize
);
649 assert(_gdtSize
% sizeof(zero
) == 0);
650 for (Addr gdtCurrent
= _gdtStart
;
651 gdtCurrent
< _gdtStart
+ _gdtSize
; gdtCurrent
+= sizeof(zero
)) {
652 initVirtMem
.write(gdtCurrent
, zero
);
655 // Set up the vsyscall page for this process.
656 allocateMem(vsyscallPage
.base
, vsyscallPage
.size
);
657 uint8_t vsyscallBlob
[] = {
661 0x89, 0xe5, // mov %esp, %ebp
662 0x0f, 0x34 // sysenter
664 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
,
665 vsyscallBlob
, sizeof(vsyscallBlob
));
667 uint8_t vsysexitBlob
[] = {
673 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsysexitOffset
,
674 vsysexitBlob
, sizeof(vsysexitBlob
));
676 for (int i
= 0; i
< contextIds
.size(); i
++) {
677 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
679 SegAttr dataAttr
= 0;
681 dataAttr
.unusable
= 0;
682 dataAttr
.defaultSize
= 1;
683 dataAttr
.longMode
= 0;
685 dataAttr
.granularity
= 1;
686 dataAttr
.present
= 1;
688 dataAttr
.writable
= 1;
689 dataAttr
.readable
= 1;
690 dataAttr
.expandDown
= 0;
693 // Initialize the segment registers.
694 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
695 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
696 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
697 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
698 tc
->setMiscRegNoEffect(MISCREG_SEG_SEL(seg
), 0xB);
699 tc
->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg
), (uint32_t)(-1));
705 csAttr
.defaultSize
= 1;
708 csAttr
.granularity
= 1;
713 csAttr
.expandDown
= 0;
716 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
718 tc
->setMiscRegNoEffect(MISCREG_TSG_BASE
, _gdtStart
);
719 tc
->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE
, _gdtStart
);
720 tc
->setMiscRegNoEffect(MISCREG_TSG_LIMIT
, _gdtStart
+ _gdtSize
- 1);
722 // Set the LDT selector to 0 to deactivate it.
723 tc
->setMiscRegNoEffect(MISCREG_TSL
, 0);
726 efer
.sce
= 1; // Enable system call extensions.
727 efer
.lme
= 1; // Enable long mode.
728 efer
.lma
= 0; // Deactivate long mode.
729 efer
.nxe
= 1; // Enable nx support.
730 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
731 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
732 tc
->setMiscReg(MISCREG_EFER
, efer
);
734 // Set up the registers that describe the operating mode.
736 cr0
.pg
= 1; // Turn on paging.
737 cr0
.cd
= 0; // Don't disable caching.
738 cr0
.nw
= 0; // This is bit is defined to be ignored.
739 cr0
.am
= 0; // No alignment checking
740 cr0
.wp
= 0; // Supervisor mode can write read only pages
742 cr0
.et
= 1; // This should always be 1
743 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
744 // would be pointless.
745 cr0
.em
= 0; // Allow x87 instructions to execute natively.
746 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
747 // setting it to one.
748 cr0
.pe
= 1; // We're definitely in protected mode.
749 tc
->setMiscReg(MISCREG_CR0
, cr0
);
751 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
755 template<class IntType
>
757 X86Process::argsInit(int pageSize
,
758 std::vector
<AuxVector
<IntType
> > extraAuxvs
)
760 int intSize
= sizeof(IntType
);
762 std::vector
<AuxVector
<IntType
>> auxv
= extraAuxvs
;
770 // We want 16 byte alignment
774 X86_OnboardFPU
= 1 << 0,
775 X86_VirtualModeExtensions
= 1 << 1,
776 X86_DebuggingExtensions
= 1 << 2,
777 X86_PageSizeExtensions
= 1 << 3,
779 X86_TimeStampCounter
= 1 << 4,
780 X86_ModelSpecificRegisters
= 1 << 5,
781 X86_PhysicalAddressExtensions
= 1 << 6,
782 X86_MachineCheckExtensions
= 1 << 7,
784 X86_CMPXCHG8Instruction
= 1 << 8,
785 X86_OnboardAPIC
= 1 << 9,
786 X86_SYSENTER_SYSEXIT
= 1 << 11,
788 X86_MemoryTypeRangeRegisters
= 1 << 12,
789 X86_PageGlobalEnable
= 1 << 13,
790 X86_MachineCheckArchitecture
= 1 << 14,
791 X86_CMOVInstruction
= 1 << 15,
793 X86_PageAttributeTable
= 1 << 16,
794 X86_36BitPSEs
= 1 << 17,
795 X86_ProcessorSerialNumber
= 1 << 18,
796 X86_CLFLUSHInstruction
= 1 << 19,
798 X86_DebugTraceStore
= 1 << 21,
799 X86_ACPIViaMSR
= 1 << 22,
800 X86_MultimediaExtensions
= 1 << 23,
802 X86_FXSAVE_FXRSTOR
= 1 << 24,
803 X86_StreamingSIMDExtensions
= 1 << 25,
804 X86_StreamingSIMDExtensions2
= 1 << 26,
805 X86_CPUSelfSnoop
= 1 << 27,
807 X86_HyperThreading
= 1 << 28,
808 X86_AutomaticClockControl
= 1 << 29,
809 X86_IA64Processor
= 1 << 30
812 // Setup the auxiliary vectors. These will already have endian
813 // conversion. Auxiliary vectors are loaded only for elf formatted
814 // executables; the auxv is responsible for passing information from
815 // the OS to the interpreter.
816 ElfObject
* elfObject
= dynamic_cast<ElfObject
*>(objFile
);
820 X86_VirtualModeExtensions
|
821 X86_DebuggingExtensions
|
822 X86_PageSizeExtensions
|
823 X86_TimeStampCounter
|
824 X86_ModelSpecificRegisters
|
825 X86_PhysicalAddressExtensions
|
826 X86_MachineCheckExtensions
|
827 X86_CMPXCHG8Instruction
|
829 X86_SYSENTER_SYSEXIT
|
830 X86_MemoryTypeRangeRegisters
|
831 X86_PageGlobalEnable
|
832 X86_MachineCheckArchitecture
|
833 X86_CMOVInstruction
|
834 X86_PageAttributeTable
|
836 // X86_ProcessorSerialNumber |
837 X86_CLFLUSHInstruction
|
838 // X86_DebugTraceStore |
840 X86_MultimediaExtensions
|
842 X86_StreamingSIMDExtensions
|
843 X86_StreamingSIMDExtensions2
|
844 // X86_CPUSelfSnoop |
845 // X86_HyperThreading |
846 // X86_AutomaticClockControl |
847 // X86_IA64Processor |
850 // Bits which describe the system hardware capabilities
851 // XXX Figure out what these should be
852 auxv
.emplace_back(M5_AT_HWCAP
, features
);
853 // The system page size
854 auxv
.emplace_back(M5_AT_PAGESZ
, X86ISA::PageBytes
);
855 // Frequency at which times() increments
856 // Defined to be 100 in the kernel source.
857 auxv
.emplace_back(M5_AT_CLKTCK
, 100);
858 // This is the virtual address of the program header tables if they
859 // appear in the executable image.
860 auxv
.emplace_back(M5_AT_PHDR
, elfObject
->programHeaderTable());
861 // This is the size of a program header entry from the elf file.
862 auxv
.emplace_back(M5_AT_PHENT
, elfObject
->programHeaderSize());
863 // This is the number of program headers from the original elf file.
864 auxv
.emplace_back(M5_AT_PHNUM
, elfObject
->programHeaderCount());
865 // This is the base address of the ELF interpreter; it should be
866 // zero for static executables or contain the base address for
867 // dynamic executables.
868 auxv
.emplace_back(M5_AT_BASE
, getBias());
869 // XXX Figure out what this should be.
870 auxv
.emplace_back(M5_AT_FLAGS
, 0);
871 // The entry point to the program
872 auxv
.emplace_back(M5_AT_ENTRY
, objFile
->entryPoint());
873 // Different user and group IDs
874 auxv
.emplace_back(M5_AT_UID
, uid());
875 auxv
.emplace_back(M5_AT_EUID
, euid());
876 auxv
.emplace_back(M5_AT_GID
, gid());
877 auxv
.emplace_back(M5_AT_EGID
, egid());
878 // Whether to enable "secure mode" in the executable
879 auxv
.emplace_back(M5_AT_SECURE
, 0);
880 // The address of 16 "random" bytes.
881 auxv
.emplace_back(M5_AT_RANDOM
, 0);
882 // The name of the program
883 auxv
.emplace_back(M5_AT_EXECFN
, 0);
884 // The platform string
885 auxv
.emplace_back(M5_AT_PLATFORM
, 0);
888 // Figure out how big the initial stack needs to be
890 // A sentry NULL void pointer at the top of the stack.
891 int sentry_size
= intSize
;
893 // This is the name of the file which is present on the initial stack
894 // It's purpose is to let the user space linker examine the original file.
895 int file_name_size
= filename
.size() + 1;
897 const int numRandomBytes
= 16;
898 int aux_data_size
= numRandomBytes
;
900 string platform
= "x86_64";
901 aux_data_size
+= platform
.size() + 1;
903 int env_data_size
= 0;
904 for (int i
= 0; i
< envp
.size(); ++i
)
905 env_data_size
+= envp
[i
].size() + 1;
906 int arg_data_size
= 0;
907 for (int i
= 0; i
< argv
.size(); ++i
)
908 arg_data_size
+= argv
[i
].size() + 1;
910 // The info_block needs to be padded so its size is a multiple of the
911 // alignment mask. Also, it appears that there needs to be at least some
912 // padding, so if the size is already a multiple, we need to increase it
914 int base_info_block_size
=
915 sentry_size
+ file_name_size
+ env_data_size
+ arg_data_size
;
917 int info_block_size
= roundUp(base_info_block_size
, align
);
919 int info_block_padding
= info_block_size
- base_info_block_size
;
921 // Each auxiliary vector is two 8 byte words
922 int aux_array_size
= intSize
* 2 * (auxv
.size() + 1);
924 int envp_array_size
= intSize
* (envp
.size() + 1);
925 int argv_array_size
= intSize
* (argv
.size() + 1);
927 int argc_size
= intSize
;
929 // Figure out the size of the contents of the actual initial frame
936 // There needs to be padding after the auxiliary vector data so that the
937 // very bottom of the stack is aligned properly.
938 int partial_size
= frame_size
+ aux_data_size
;
939 int aligned_partial_size
= roundUp(partial_size
, align
);
940 int aux_padding
= aligned_partial_size
- partial_size
;
948 Addr stack_base
= memState
->getStackBase();
950 Addr stack_min
= stack_base
- space_needed
;
951 stack_min
= roundDown(stack_min
, align
);
953 unsigned stack_size
= stack_base
- stack_min
;
954 stack_size
= roundUp(stack_size
, pageSize
);
955 memState
->setStackSize(stack_size
);
958 Addr stack_end
= roundDown(stack_base
- stack_size
, pageSize
);
960 DPRINTF(Stack
, "Mapping the stack: 0x%x %dB\n", stack_end
, stack_size
);
961 allocateMem(stack_end
, stack_size
);
963 // map out initial stack contents
964 IntType sentry_base
= stack_base
- sentry_size
;
965 IntType file_name_base
= sentry_base
- file_name_size
;
966 IntType env_data_base
= file_name_base
- env_data_size
;
967 IntType arg_data_base
= env_data_base
- arg_data_size
;
968 IntType aux_data_base
= arg_data_base
- info_block_padding
- aux_data_size
;
969 IntType auxv_array_base
= aux_data_base
- aux_array_size
- aux_padding
;
970 IntType envp_array_base
= auxv_array_base
- envp_array_size
;
971 IntType argv_array_base
= envp_array_base
- argv_array_size
;
972 IntType argc_base
= argv_array_base
- argc_size
;
974 DPRINTF(Stack
, "The addresses of items on the initial stack:\n");
975 DPRINTF(Stack
, "0x%x - file name\n", file_name_base
);
976 DPRINTF(Stack
, "0x%x - env data\n", env_data_base
);
977 DPRINTF(Stack
, "0x%x - arg data\n", arg_data_base
);
978 DPRINTF(Stack
, "0x%x - aux data\n", aux_data_base
);
979 DPRINTF(Stack
, "0x%x - auxv array\n", auxv_array_base
);
980 DPRINTF(Stack
, "0x%x - envp array\n", envp_array_base
);
981 DPRINTF(Stack
, "0x%x - argv array\n", argv_array_base
);
982 DPRINTF(Stack
, "0x%x - argc \n", argc_base
);
983 DPRINTF(Stack
, "0x%x - stack min\n", stack_min
);
985 // write contents to stack
988 IntType argc
= argv
.size();
989 IntType guestArgc
= htole(argc
);
991 // Write out the sentry void *
992 IntType sentry_NULL
= 0;
993 initVirtMem
.writeBlob(sentry_base
, &sentry_NULL
, sentry_size
);
995 // Write the file name
996 initVirtMem
.writeString(file_name_base
, filename
.c_str());
998 // Fix up the aux vectors which point to data
999 assert(auxv
[auxv
.size() - 3].type
== M5_AT_RANDOM
);
1000 auxv
[auxv
.size() - 3].val
= aux_data_base
;
1001 assert(auxv
[auxv
.size() - 2].type
== M5_AT_EXECFN
);
1002 auxv
[auxv
.size() - 2].val
= argv_array_base
;
1003 assert(auxv
[auxv
.size() - 1].type
== M5_AT_PLATFORM
);
1004 auxv
[auxv
.size() - 1].val
= aux_data_base
+ numRandomBytes
;
1007 // Copy the aux stuff
1008 Addr auxv_array_end
= auxv_array_base
;
1009 for (const auto &aux
: auxv
) {
1010 initVirtMem
.write(auxv_array_end
, aux
, GuestByteOrder
);
1011 auxv_array_end
+= sizeof(aux
);
1013 // Write out the terminating zeroed auxiliary vector
1014 const AuxVector
<uint64_t> zero(0, 0);
1015 initVirtMem
.write(auxv_array_end
, zero
);
1016 auxv_array_end
+= sizeof(zero
);
1018 initVirtMem
.writeString(aux_data_base
, platform
.c_str());
1020 copyStringArray(envp
, envp_array_base
, env_data_base
,
1021 LittleEndianByteOrder
, initVirtMem
);
1022 copyStringArray(argv
, argv_array_base
, arg_data_base
,
1023 LittleEndianByteOrder
, initVirtMem
);
1025 initVirtMem
.writeBlob(argc_base
, &guestArgc
, intSize
);
1027 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
1028 // Set the stack pointer register
1029 tc
->setIntReg(StackPointerReg
, stack_min
);
1031 // There doesn't need to be any segment base added in since we're dealing
1032 // with the flat segmentation model.
1033 tc
->pcState(getStartPC());
1035 // Align the "stack_min" to a page boundary.
1036 memState
->setStackMin(roundDown(stack_min
, pageSize
));
1040 X86_64Process::argsInit(int pageSize
)
1042 std::vector
<AuxVector
<uint64_t> > extraAuxvs
;
1043 extraAuxvs
.emplace_back(M5_AT_SYSINFO_EHDR
, vsyscallPage
.base
);
1044 X86Process::argsInit
<uint64_t>(pageSize
, extraAuxvs
);
1048 I386Process::argsInit(int pageSize
)
1050 std::vector
<AuxVector
<uint32_t> > extraAuxvs
;
1051 //Tell the binary where the vsyscall part of the vsyscall page is.
1052 extraAuxvs
.emplace_back(M5_AT_SYSINFO
,
1053 vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
);
1054 extraAuxvs
.emplace_back(M5_AT_SYSINFO_EHDR
, vsyscallPage
.base
);
1055 X86Process::argsInit
<uint32_t>(pageSize
, extraAuxvs
);
1059 X86Process::setSyscallReturn(ThreadContext
*tc
, SyscallReturn retval
)
1061 tc
->setIntReg(INTREG_RAX
, retval
.encodedValue());
1065 X86_64Process::getSyscallArg(ThreadContext
*tc
, int &i
)
1067 assert(i
< NumArgumentRegs
);
1068 return tc
->readIntReg(ArgumentReg
[i
++]);
1072 X86_64Process::setSyscallArg(ThreadContext
*tc
, int i
, RegVal val
)
1074 assert(i
< NumArgumentRegs
);
1075 return tc
->setIntReg(ArgumentReg
[i
], val
);
1079 X86_64Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1080 Process
*p
, RegVal flags
)
1082 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1083 ((X86_64Process
*)p
)->vsyscallPage
= vsyscallPage
;
1087 I386Process::getSyscallArg(ThreadContext
*tc
, int &i
)
1089 assert(i
< NumArgumentRegs32
);
1090 return tc
->readIntReg(ArgumentReg32
[i
++]);
1094 I386Process::getSyscallArg(ThreadContext
*tc
, int &i
, int width
)
1096 assert(width
== 32 || width
== 64);
1097 assert(i
< NumArgumentRegs
);
1098 uint64_t retVal
= tc
->readIntReg(ArgumentReg32
[i
++]) & mask(32);
1100 retVal
|= ((uint64_t)tc
->readIntReg(ArgumentReg
[i
++]) << 32);
1105 I386Process::setSyscallArg(ThreadContext
*tc
, int i
, RegVal val
)
1107 assert(i
< NumArgumentRegs
);
1108 return tc
->setIntReg(ArgumentReg
[i
], val
);
1112 I386Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1113 Process
*p
, RegVal flags
)
1115 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1116 ((I386Process
*)p
)->vsyscallPage
= vsyscallPage
;