2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2007 The Hewlett-Packard Development Company
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 #include "arch/x86/process.hh"
50 #include "arch/x86/isa_traits.hh"
51 #include "arch/x86/regs/misc.hh"
52 #include "arch/x86/regs/segment.hh"
53 #include "arch/x86/system.hh"
54 #include "arch/x86/types.hh"
55 #include "base/loader/elf_object.hh"
56 #include "base/loader/object_file.hh"
57 #include "base/logging.hh"
58 #include "base/trace.hh"
59 #include "cpu/thread_context.hh"
60 #include "debug/Stack.hh"
61 #include "mem/multi_level_page_table.hh"
62 #include "mem/page_table.hh"
63 #include "params/Process.hh"
64 #include "sim/aux_vector.hh"
65 #include "sim/process_impl.hh"
66 #include "sim/syscall_desc.hh"
67 #include "sim/syscall_return.hh"
68 #include "sim/system.hh"
71 using namespace X86ISA
;
73 static const int ArgumentReg
[] = {
77 // This argument register is r10 for syscalls and rcx for C.
84 static const int NumArgumentRegs M5_VAR_USED
=
85 sizeof(ArgumentReg
) / sizeof(const int);
87 static const int ArgumentReg32
[] = {
96 static const int NumArgumentRegs32 M5_VAR_USED
=
97 sizeof(ArgumentReg
) / sizeof(const int);
99 template class MultiLevelPageTable
<LongModePTE
<47, 39>,
102 LongModePTE
<20, 12> >;
103 typedef MultiLevelPageTable
<LongModePTE
<47, 39>,
106 LongModePTE
<20, 12> > ArchPageTable
;
108 X86Process::X86Process(ProcessParams
*params
, ObjectFile
*objFile
,
109 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
110 : Process(params
, params
->useArchPT
?
111 static_cast<EmulationPageTable
*>(
112 new ArchPageTable(params
->name
, params
->pid
,
113 params
->system
, PageBytes
)) :
114 new EmulationPageTable(params
->name
, params
->pid
,
117 syscallDescs(_syscallDescs
), numSyscallDescs(_numSyscallDescs
)
121 void X86Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
122 Process
*p
, RegVal flags
)
124 Process::clone(old_tc
, new_tc
, p
, flags
);
125 X86Process
*process
= (X86Process
*)p
;
129 X86_64Process::X86_64Process(ProcessParams
*params
, ObjectFile
*objFile
,
130 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
131 : X86Process(params
, objFile
, _syscallDescs
, _numSyscallDescs
)
134 vsyscallPage
.base
= 0xffffffffff600000ULL
;
135 vsyscallPage
.size
= PageBytes
;
136 vsyscallPage
.vtimeOffset
= 0x400;
137 vsyscallPage
.vgettimeofdayOffset
= 0x0;
139 Addr brk_point
= roundUp(image
.maxAddr(), PageBytes
);
140 Addr stack_base
= 0x7FFFFFFFF000ULL
;
141 Addr max_stack_size
= 8 * 1024 * 1024;
142 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
143 Addr mmap_end
= 0x7FFFF7FFF000ULL
;
145 memState
= make_shared
<MemState
>(brk_point
, stack_base
, max_stack_size
,
146 next_thread_stack_base
, mmap_end
);
150 I386Process::I386Process(ProcessParams
*params
, ObjectFile
*objFile
,
151 SyscallDesc
*_syscallDescs
, int _numSyscallDescs
)
152 : X86Process(params
, objFile
, _syscallDescs
, _numSyscallDescs
)
155 panic("KVM CPU model does not support 32 bit processes");
157 _gdtStart
= ULL(0xffffd000);
158 _gdtSize
= PageBytes
;
160 vsyscallPage
.base
= 0xffffe000ULL
;
161 vsyscallPage
.size
= PageBytes
;
162 vsyscallPage
.vsyscallOffset
= 0x400;
163 vsyscallPage
.vsysexitOffset
= 0x410;
165 Addr brk_point
= roundUp(image
.maxAddr(), PageBytes
);
166 Addr stack_base
= _gdtStart
;
167 Addr max_stack_size
= 8 * 1024 * 1024;
168 Addr next_thread_stack_base
= stack_base
- max_stack_size
;
169 Addr mmap_end
= 0xB7FFF000ULL
;
171 memState
= make_shared
<MemState
>(brk_point
, stack_base
, max_stack_size
,
172 next_thread_stack_base
, mmap_end
);
176 X86Process::getDesc(int callnum
)
178 if (callnum
< 0 || callnum
>= numSyscallDescs
)
180 return &syscallDescs
[callnum
];
184 X86_64Process::initState()
186 X86Process::initState();
193 // Set up the vsyscall page for this process.
194 allocateMem(vsyscallPage
.base
, vsyscallPage
.size
);
195 uint8_t vtimeBlob
[] = {
196 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax
197 0x0f,0x05, // syscall
200 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vtimeOffset
,
201 vtimeBlob
, sizeof(vtimeBlob
));
203 uint8_t vgettimeofdayBlob
[] = {
204 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax
205 0x0f,0x05, // syscall
208 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vgettimeofdayOffset
,
209 vgettimeofdayBlob
, sizeof(vgettimeofdayBlob
));
212 PortProxy physProxy
= system
->physProxy
;
214 Addr syscallCodePhysAddr
= system
->allocPhysPages(1);
215 Addr gdtPhysAddr
= system
->allocPhysPages(1);
216 Addr idtPhysAddr
= system
->allocPhysPages(1);
217 Addr istPhysAddr
= system
->allocPhysPages(1);
218 Addr tssPhysAddr
= system
->allocPhysPages(1);
219 Addr pfHandlerPhysAddr
= system
->allocPhysPages(1);
224 uint8_t numGDTEntries
= 0;
225 uint64_t nullDescriptor
= 0;
226 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
230 SegDescriptor initDesc
= 0;
231 initDesc
.type
.codeOrData
= 0; // code or data type
232 initDesc
.type
.c
= 0; // conforming
233 initDesc
.type
.r
= 1; // readable
234 initDesc
.dpl
= 0; // privilege
235 initDesc
.p
= 1; // present
236 initDesc
.l
= 1; // longmode - 64 bit
237 initDesc
.d
= 0; // operand size
238 initDesc
.s
= 1; // system segment
239 initDesc
.limit
= 0xFFFFFFFF;
242 //64 bit code segment
243 SegDescriptor csLowPLDesc
= initDesc
;
244 csLowPLDesc
.type
.codeOrData
= 1;
246 uint64_t csLowPLDescVal
= csLowPLDesc
;
247 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
252 SegSelector csLowPL
= 0;
253 csLowPL
.si
= numGDTEntries
- 1;
256 //64 bit data segment
257 SegDescriptor dsLowPLDesc
= initDesc
;
258 dsLowPLDesc
.type
.codeOrData
= 0;
260 uint64_t dsLowPLDescVal
= dsLowPLDesc
;
261 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
266 SegSelector dsLowPL
= 0;
267 dsLowPL
.si
= numGDTEntries
- 1;
270 //64 bit data segment
271 SegDescriptor dsDesc
= initDesc
;
272 dsDesc
.type
.codeOrData
= 0;
274 uint64_t dsDescVal
= dsDesc
;
275 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
281 ds
.si
= numGDTEntries
- 1;
284 //64 bit code segment
285 SegDescriptor csDesc
= initDesc
;
286 csDesc
.type
.codeOrData
= 1;
288 uint64_t csDescVal
= csDesc
;
289 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
295 cs
.si
= numGDTEntries
- 1;
298 SegSelector scall
= 0;
299 scall
.si
= csLowPL
.si
;
302 SegSelector sret
= 0;
303 sret
.si
= dsLowPL
.si
;
306 /* In long mode the TSS has been extended to 16 Bytes */
307 TSSlow TSSDescLow
= 0;
308 TSSDescLow
.type
= 0xB;
309 TSSDescLow
.dpl
= 0; // Privelege level 0
310 TSSDescLow
.p
= 1; // Present
311 TSSDescLow
.limit
= 0xFFFFFFFF;
312 TSSDescLow
.base
= bits(TSSVirtAddr
, 31, 0);
314 TSShigh TSSDescHigh
= 0;
315 TSSDescHigh
.base
= bits(TSSVirtAddr
, 63, 32);
320 } tssDescVal
= {TSSDescLow
, TSSDescHigh
};
322 physProxy
.writeBlob(gdtPhysAddr
+ numGDTEntries
* 8,
323 &tssDescVal
, sizeof(tssDescVal
));
327 SegSelector tssSel
= 0;
328 tssSel
.si
= numGDTEntries
- 1;
330 uint64_t tss_base_addr
= (TSSDescHigh
.base
<< 32) | TSSDescLow
.base
;
331 uint64_t tss_limit
= TSSDescLow
.limit
;
333 SegAttr tss_attr
= 0;
335 tss_attr
.type
= TSSDescLow
.type
;
336 tss_attr
.dpl
= TSSDescLow
.dpl
;
337 tss_attr
.present
= TSSDescLow
.p
;
338 tss_attr
.granularity
= TSSDescLow
.g
;
339 tss_attr
.unusable
= 0;
341 for (int i
= 0; i
< contextIds
.size(); i
++) {
342 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
344 tc
->setMiscReg(MISCREG_CS
, cs
);
345 tc
->setMiscReg(MISCREG_DS
, ds
);
346 tc
->setMiscReg(MISCREG_ES
, ds
);
347 tc
->setMiscReg(MISCREG_FS
, ds
);
348 tc
->setMiscReg(MISCREG_GS
, ds
);
349 tc
->setMiscReg(MISCREG_SS
, ds
);
352 tc
->setMiscReg(MISCREG_TSL
, 0);
356 tc
->setMiscReg(MISCREG_TSL_ATTR
, tslAttr
);
358 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
359 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 8 * numGDTEntries
- 1);
361 tc
->setMiscReg(MISCREG_TR
, tssSel
);
362 tc
->setMiscReg(MISCREG_TR_BASE
, tss_base_addr
);
363 tc
->setMiscReg(MISCREG_TR_EFF_BASE
, 0);
364 tc
->setMiscReg(MISCREG_TR_LIMIT
, tss_limit
);
365 tc
->setMiscReg(MISCREG_TR_ATTR
, tss_attr
);
367 //Start using longmode segments.
368 installSegDesc(tc
, SEGMENT_REG_CS
, csDesc
, true);
369 installSegDesc(tc
, SEGMENT_REG_DS
, dsDesc
, true);
370 installSegDesc(tc
, SEGMENT_REG_ES
, dsDesc
, true);
371 installSegDesc(tc
, SEGMENT_REG_FS
, dsDesc
, true);
372 installSegDesc(tc
, SEGMENT_REG_GS
, dsDesc
, true);
373 installSegDesc(tc
, SEGMENT_REG_SS
, dsDesc
, true);
376 efer
.sce
= 1; // Enable system call extensions.
377 efer
.lme
= 1; // Enable long mode.
378 efer
.lma
= 1; // Activate long mode.
379 efer
.nxe
= 0; // Enable nx support.
380 efer
.svme
= 1; // Enable svm support for now.
381 efer
.ffxsr
= 0; // Turn on fast fxsave and fxrstor.
382 tc
->setMiscReg(MISCREG_EFER
, efer
);
384 //Set up the registers that describe the operating mode.
386 cr0
.pg
= 1; // Turn on paging.
387 cr0
.cd
= 0; // Don't disable caching.
388 cr0
.nw
= 0; // This is bit is defined to be ignored.
389 cr0
.am
= 1; // No alignment checking
390 cr0
.wp
= 1; // Supervisor mode can write read only pages
392 cr0
.et
= 1; // This should always be 1
393 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
394 // would be pointless.
395 cr0
.em
= 0; // Allow x87 instructions to execute natively.
396 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
397 // setting it to one.
398 cr0
.pe
= 1; // We're definitely in protected mode.
399 tc
->setMiscReg(MISCREG_CR0
, cr0
);
402 tc
->setMiscReg(MISCREG_CR2
, cr2
);
404 CR3 cr3
= dynamic_cast<ArchPageTable
*>(pTable
)->basePtr();
405 tc
->setMiscReg(MISCREG_CR3
, cr3
);
409 cr4
.osxsave
= 1; // Enable XSAVE and Proc Extended States
410 cr4
.osxmmexcpt
= 1; // Operating System Unmasked Exception
411 cr4
.osfxsr
= 1; // Operating System FXSave/FSRSTOR Support
412 cr4
.pce
= 0; // Performance-Monitoring Counter Enable
413 cr4
.pge
= 0; // Page-Global Enable
414 cr4
.mce
= 0; // Machine Check Enable
415 cr4
.pae
= 1; // Physical-Address Extension
416 cr4
.pse
= 0; // Page Size Extensions
417 cr4
.de
= 0; // Debugging Extensions
418 cr4
.tsd
= 0; // Time Stamp Disable
419 cr4
.pvi
= 0; // Protected-Mode Virtual Interrupts
420 cr4
.vme
= 0; // Virtual-8086 Mode Extensions
422 tc
->setMiscReg(MISCREG_CR4
, cr4
);
425 tc
->setMiscReg(MISCREG_CR8
, cr8
);
427 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
429 tc
->setMiscReg(MISCREG_APIC_BASE
, 0xfee00900);
431 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTVirtAddr
);
432 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 0xffff);
434 tc
->setMiscReg(MISCREG_IDTR_BASE
, IDTVirtAddr
);
435 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
437 /* enabling syscall and sysret */
438 RegVal star
= ((RegVal
)sret
<< 48) | ((RegVal
)scall
<< 32);
439 tc
->setMiscReg(MISCREG_STAR
, star
);
440 RegVal lstar
= (RegVal
)syscallCodeVirtAddr
;
441 tc
->setMiscReg(MISCREG_LSTAR
, lstar
);
442 RegVal sfmask
= (1 << 8) | (1 << 10); // TF | DF
443 tc
->setMiscReg(MISCREG_SF_MASK
, sfmask
);
446 /* Set up the content of the TSS and write it to physical memory. */
449 uint32_t reserved0
; // +00h
450 uint32_t RSP0_low
; // +04h
451 uint32_t RSP0_high
; // +08h
452 uint32_t RSP1_low
; // +0Ch
453 uint32_t RSP1_high
; // +10h
454 uint32_t RSP2_low
; // +14h
455 uint32_t RSP2_high
; // +18h
456 uint32_t reserved1
; // +1Ch
457 uint32_t reserved2
; // +20h
458 uint32_t IST1_low
; // +24h
459 uint32_t IST1_high
; // +28h
460 uint32_t IST2_low
; // +2Ch
461 uint32_t IST2_high
; // +30h
462 uint32_t IST3_low
; // +34h
463 uint32_t IST3_high
; // +38h
464 uint32_t IST4_low
; // +3Ch
465 uint32_t IST4_high
; // +40h
466 uint32_t IST5_low
; // +44h
467 uint32_t IST5_high
; // +48h
468 uint32_t IST6_low
; // +4Ch
469 uint32_t IST6_high
; // +50h
470 uint32_t IST7_low
; // +54h
471 uint32_t IST7_high
; // +58h
472 uint32_t reserved3
; // +5Ch
473 uint32_t reserved4
; // +60h
474 uint16_t reserved5
; // +64h
475 uint16_t IO_MapBase
; // +66h
478 /** setting Interrupt Stack Table */
479 uint64_t IST_start
= ISTVirtAddr
+ PageBytes
;
480 tss
.IST1_low
= IST_start
;
481 tss
.IST1_high
= IST_start
>> 32;
482 tss
.RSP0_low
= tss
.IST1_low
;
483 tss
.RSP0_high
= tss
.IST1_high
;
484 tss
.RSP1_low
= tss
.IST1_low
;
485 tss
.RSP1_high
= tss
.IST1_high
;
486 tss
.RSP2_low
= tss
.IST1_low
;
487 tss
.RSP2_high
= tss
.IST1_high
;
488 physProxy
.writeBlob(tssPhysAddr
, &tss
, sizeof(tss
));
490 /* Setting IDT gates */
491 GateDescriptorLow PFGateLow
= 0;
492 PFGateLow
.offsetHigh
= bits(PFHandlerVirtAddr
, 31, 16);
493 PFGateLow
.offsetLow
= bits(PFHandlerVirtAddr
, 15, 0);
494 PFGateLow
.selector
= csLowPL
;
497 PFGateLow
.type
= 0xe; // gate interrupt type
498 PFGateLow
.IST
= 0; // setting IST to 0 and using RSP0
500 GateDescriptorHigh PFGateHigh
= 0;
501 PFGateHigh
.offset
= bits(PFHandlerVirtAddr
, 63, 32);
506 } PFGate
= {PFGateLow
, PFGateHigh
};
508 physProxy
.writeBlob(idtPhysAddr
+ 0xE0, &PFGate
, sizeof(PFGate
));
510 /* System call handler */
511 uint8_t syscallBlob
[] = {
512 // mov %rax, (0xffffc90000005600)
513 0x48, 0xa3, 0x00, 0x60, 0x00,
514 0x00, 0x00, 0xc9, 0xff, 0xff,
519 physProxy
.writeBlob(syscallCodePhysAddr
,
520 syscallBlob
, sizeof(syscallBlob
));
522 /** Page fault handler */
523 uint8_t faultBlob
[] = {
524 // mov %rax, (0xffffc90000005700)
525 0x48, 0xa3, 0x00, 0x61, 0x00,
526 0x00, 0x00, 0xc9, 0xff, 0xff,
527 // add $0x8, %rsp # skip error
528 0x48, 0x83, 0xc4, 0x08,
533 physProxy
.writeBlob(pfHandlerPhysAddr
, faultBlob
, sizeof(faultBlob
));
535 /* Syscall handler */
536 pTable
->map(syscallCodeVirtAddr
, syscallCodePhysAddr
,
539 pTable
->map(GDTVirtAddr
, gdtPhysAddr
, PageBytes
, false);
541 pTable
->map(IDTVirtAddr
, idtPhysAddr
, PageBytes
, false);
543 pTable
->map(TSSVirtAddr
, tssPhysAddr
, PageBytes
, false);
545 pTable
->map(ISTVirtAddr
, istPhysAddr
, PageBytes
, false);
547 pTable
->map(PFHandlerVirtAddr
, pfHandlerPhysAddr
, PageBytes
, false);
548 /* MMIO region for m5ops */
549 pTable
->map(MMIORegionVirtAddr
, MMIORegionPhysAddr
,
550 16 * PageBytes
, false);
552 for (int i
= 0; i
< contextIds
.size(); i
++) {
553 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
555 SegAttr dataAttr
= 0;
557 dataAttr
.unusable
= 0;
558 dataAttr
.defaultSize
= 1;
559 dataAttr
.longMode
= 1;
561 dataAttr
.granularity
= 1;
562 dataAttr
.present
= 1;
564 dataAttr
.writable
= 1;
565 dataAttr
.readable
= 1;
566 dataAttr
.expandDown
= 0;
569 // Initialize the segment registers.
570 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
571 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
572 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
573 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
579 csAttr
.defaultSize
= 0;
582 csAttr
.granularity
= 1;
587 csAttr
.expandDown
= 0;
590 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
593 efer
.sce
= 1; // Enable system call extensions.
594 efer
.lme
= 1; // Enable long mode.
595 efer
.lma
= 1; // Activate long mode.
596 efer
.nxe
= 1; // Enable nx support.
597 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
598 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
599 tc
->setMiscReg(MISCREG_EFER
, efer
);
601 // Set up the registers that describe the operating mode.
603 cr0
.pg
= 1; // Turn on paging.
604 cr0
.cd
= 0; // Don't disable caching.
605 cr0
.nw
= 0; // This is bit is defined to be ignored.
606 cr0
.am
= 0; // No alignment checking
607 cr0
.wp
= 0; // Supervisor mode can write read only pages
609 cr0
.et
= 1; // This should always be 1
610 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
611 // would be pointless.
612 cr0
.em
= 0; // Allow x87 instructions to execute natively.
613 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
614 // setting it to one.
615 cr0
.pe
= 1; // We're definitely in protected mode.
616 tc
->setMiscReg(MISCREG_CR0
, cr0
);
618 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
624 I386Process::initState()
626 X86Process::initState();
631 * Set up a GDT for this process. The whole GDT wouldn't really be for
632 * this process, but the only parts we care about are.
634 allocateMem(_gdtStart
, _gdtSize
);
636 assert(_gdtSize
% sizeof(zero
) == 0);
637 for (Addr gdtCurrent
= _gdtStart
;
638 gdtCurrent
< _gdtStart
+ _gdtSize
; gdtCurrent
+= sizeof(zero
)) {
639 initVirtMem
.write(gdtCurrent
, zero
);
642 // Set up the vsyscall page for this process.
643 allocateMem(vsyscallPage
.base
, vsyscallPage
.size
);
644 uint8_t vsyscallBlob
[] = {
648 0x89, 0xe5, // mov %esp, %ebp
649 0x0f, 0x34 // sysenter
651 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
,
652 vsyscallBlob
, sizeof(vsyscallBlob
));
654 uint8_t vsysexitBlob
[] = {
660 initVirtMem
.writeBlob(vsyscallPage
.base
+ vsyscallPage
.vsysexitOffset
,
661 vsysexitBlob
, sizeof(vsysexitBlob
));
663 for (int i
= 0; i
< contextIds
.size(); i
++) {
664 ThreadContext
* tc
= system
->getThreadContext(contextIds
[i
]);
666 SegAttr dataAttr
= 0;
668 dataAttr
.unusable
= 0;
669 dataAttr
.defaultSize
= 1;
670 dataAttr
.longMode
= 0;
672 dataAttr
.granularity
= 1;
673 dataAttr
.present
= 1;
675 dataAttr
.writable
= 1;
676 dataAttr
.readable
= 1;
677 dataAttr
.expandDown
= 0;
680 // Initialize the segment registers.
681 for (int seg
= 0; seg
< NUM_SEGMENTREGS
; seg
++) {
682 tc
->setMiscRegNoEffect(MISCREG_SEG_BASE(seg
), 0);
683 tc
->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg
), 0);
684 tc
->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg
), dataAttr
);
685 tc
->setMiscRegNoEffect(MISCREG_SEG_SEL(seg
), 0xB);
686 tc
->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg
), (uint32_t)(-1));
692 csAttr
.defaultSize
= 1;
695 csAttr
.granularity
= 1;
700 csAttr
.expandDown
= 0;
703 tc
->setMiscRegNoEffect(MISCREG_CS_ATTR
, csAttr
);
705 tc
->setMiscRegNoEffect(MISCREG_TSG_BASE
, _gdtStart
);
706 tc
->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE
, _gdtStart
);
707 tc
->setMiscRegNoEffect(MISCREG_TSG_LIMIT
, _gdtStart
+ _gdtSize
- 1);
709 // Set the LDT selector to 0 to deactivate it.
710 tc
->setMiscRegNoEffect(MISCREG_TSL
, 0);
713 efer
.sce
= 1; // Enable system call extensions.
714 efer
.lme
= 1; // Enable long mode.
715 efer
.lma
= 0; // Deactivate long mode.
716 efer
.nxe
= 1; // Enable nx support.
717 efer
.svme
= 0; // Disable svm support for now. It isn't implemented.
718 efer
.ffxsr
= 1; // Turn on fast fxsave and fxrstor.
719 tc
->setMiscReg(MISCREG_EFER
, efer
);
721 // Set up the registers that describe the operating mode.
723 cr0
.pg
= 1; // Turn on paging.
724 cr0
.cd
= 0; // Don't disable caching.
725 cr0
.nw
= 0; // This is bit is defined to be ignored.
726 cr0
.am
= 0; // No alignment checking
727 cr0
.wp
= 0; // Supervisor mode can write read only pages
729 cr0
.et
= 1; // This should always be 1
730 cr0
.ts
= 0; // We don't do task switching, so causing fp exceptions
731 // would be pointless.
732 cr0
.em
= 0; // Allow x87 instructions to execute natively.
733 cr0
.mp
= 1; // This doesn't really matter, but the manual suggests
734 // setting it to one.
735 cr0
.pe
= 1; // We're definitely in protected mode.
736 tc
->setMiscReg(MISCREG_CR0
, cr0
);
738 tc
->setMiscReg(MISCREG_MXCSR
, 0x1f80);
742 template<class IntType
>
744 X86Process::argsInit(int pageSize
,
745 std::vector
<AuxVector
<IntType
> > extraAuxvs
)
747 int intSize
= sizeof(IntType
);
749 std::vector
<AuxVector
<IntType
>> auxv
= extraAuxvs
;
757 // We want 16 byte alignment
761 X86_OnboardFPU
= 1 << 0,
762 X86_VirtualModeExtensions
= 1 << 1,
763 X86_DebuggingExtensions
= 1 << 2,
764 X86_PageSizeExtensions
= 1 << 3,
766 X86_TimeStampCounter
= 1 << 4,
767 X86_ModelSpecificRegisters
= 1 << 5,
768 X86_PhysicalAddressExtensions
= 1 << 6,
769 X86_MachineCheckExtensions
= 1 << 7,
771 X86_CMPXCHG8Instruction
= 1 << 8,
772 X86_OnboardAPIC
= 1 << 9,
773 X86_SYSENTER_SYSEXIT
= 1 << 11,
775 X86_MemoryTypeRangeRegisters
= 1 << 12,
776 X86_PageGlobalEnable
= 1 << 13,
777 X86_MachineCheckArchitecture
= 1 << 14,
778 X86_CMOVInstruction
= 1 << 15,
780 X86_PageAttributeTable
= 1 << 16,
781 X86_36BitPSEs
= 1 << 17,
782 X86_ProcessorSerialNumber
= 1 << 18,
783 X86_CLFLUSHInstruction
= 1 << 19,
785 X86_DebugTraceStore
= 1 << 21,
786 X86_ACPIViaMSR
= 1 << 22,
787 X86_MultimediaExtensions
= 1 << 23,
789 X86_FXSAVE_FXRSTOR
= 1 << 24,
790 X86_StreamingSIMDExtensions
= 1 << 25,
791 X86_StreamingSIMDExtensions2
= 1 << 26,
792 X86_CPUSelfSnoop
= 1 << 27,
794 X86_HyperThreading
= 1 << 28,
795 X86_AutomaticClockControl
= 1 << 29,
796 X86_IA64Processor
= 1 << 30
799 // Setup the auxiliary vectors. These will already have endian
800 // conversion. Auxiliary vectors are loaded only for elf formatted
801 // executables; the auxv is responsible for passing information from
802 // the OS to the interpreter.
803 ElfObject
* elfObject
= dynamic_cast<ElfObject
*>(objFile
);
807 X86_VirtualModeExtensions
|
808 X86_DebuggingExtensions
|
809 X86_PageSizeExtensions
|
810 X86_TimeStampCounter
|
811 X86_ModelSpecificRegisters
|
812 X86_PhysicalAddressExtensions
|
813 X86_MachineCheckExtensions
|
814 X86_CMPXCHG8Instruction
|
816 X86_SYSENTER_SYSEXIT
|
817 X86_MemoryTypeRangeRegisters
|
818 X86_PageGlobalEnable
|
819 X86_MachineCheckArchitecture
|
820 X86_CMOVInstruction
|
821 X86_PageAttributeTable
|
823 // X86_ProcessorSerialNumber |
824 X86_CLFLUSHInstruction
|
825 // X86_DebugTraceStore |
827 X86_MultimediaExtensions
|
829 X86_StreamingSIMDExtensions
|
830 X86_StreamingSIMDExtensions2
|
831 // X86_CPUSelfSnoop |
832 // X86_HyperThreading |
833 // X86_AutomaticClockControl |
834 // X86_IA64Processor |
837 // Bits which describe the system hardware capabilities
838 // XXX Figure out what these should be
839 auxv
.emplace_back(M5_AT_HWCAP
, features
);
840 // The system page size
841 auxv
.emplace_back(M5_AT_PAGESZ
, X86ISA::PageBytes
);
842 // Frequency at which times() increments
843 // Defined to be 100 in the kernel source.
844 auxv
.emplace_back(M5_AT_CLKTCK
, 100);
845 // This is the virtual address of the program header tables if they
846 // appear in the executable image.
847 auxv
.emplace_back(M5_AT_PHDR
, elfObject
->programHeaderTable());
848 // This is the size of a program header entry from the elf file.
849 auxv
.emplace_back(M5_AT_PHENT
, elfObject
->programHeaderSize());
850 // This is the number of program headers from the original elf file.
851 auxv
.emplace_back(M5_AT_PHNUM
, elfObject
->programHeaderCount());
852 // This is the base address of the ELF interpreter; it should be
853 // zero for static executables or contain the base address for
854 // dynamic executables.
855 auxv
.emplace_back(M5_AT_BASE
, getBias());
856 // XXX Figure out what this should be.
857 auxv
.emplace_back(M5_AT_FLAGS
, 0);
858 // The entry point to the program
859 auxv
.emplace_back(M5_AT_ENTRY
, objFile
->entryPoint());
860 // Different user and group IDs
861 auxv
.emplace_back(M5_AT_UID
, uid());
862 auxv
.emplace_back(M5_AT_EUID
, euid());
863 auxv
.emplace_back(M5_AT_GID
, gid());
864 auxv
.emplace_back(M5_AT_EGID
, egid());
865 // Whether to enable "secure mode" in the executable
866 auxv
.emplace_back(M5_AT_SECURE
, 0);
867 // The address of 16 "random" bytes.
868 auxv
.emplace_back(M5_AT_RANDOM
, 0);
869 // The name of the program
870 auxv
.emplace_back(M5_AT_EXECFN
, 0);
871 // The platform string
872 auxv
.emplace_back(M5_AT_PLATFORM
, 0);
875 // Figure out how big the initial stack needs to be
877 // A sentry NULL void pointer at the top of the stack.
878 int sentry_size
= intSize
;
880 // This is the name of the file which is present on the initial stack
881 // It's purpose is to let the user space linker examine the original file.
882 int file_name_size
= filename
.size() + 1;
884 const int numRandomBytes
= 16;
885 int aux_data_size
= numRandomBytes
;
887 string platform
= "x86_64";
888 aux_data_size
+= platform
.size() + 1;
890 int env_data_size
= 0;
891 for (int i
= 0; i
< envp
.size(); ++i
)
892 env_data_size
+= envp
[i
].size() + 1;
893 int arg_data_size
= 0;
894 for (int i
= 0; i
< argv
.size(); ++i
)
895 arg_data_size
+= argv
[i
].size() + 1;
897 // The info_block needs to be padded so its size is a multiple of the
898 // alignment mask. Also, it appears that there needs to be at least some
899 // padding, so if the size is already a multiple, we need to increase it
901 int base_info_block_size
=
902 sentry_size
+ file_name_size
+ env_data_size
+ arg_data_size
;
904 int info_block_size
= roundUp(base_info_block_size
, align
);
906 int info_block_padding
= info_block_size
- base_info_block_size
;
908 // Each auxiliary vector is two 8 byte words
909 int aux_array_size
= intSize
* 2 * (auxv
.size() + 1);
911 int envp_array_size
= intSize
* (envp
.size() + 1);
912 int argv_array_size
= intSize
* (argv
.size() + 1);
914 int argc_size
= intSize
;
916 // Figure out the size of the contents of the actual initial frame
923 // There needs to be padding after the auxiliary vector data so that the
924 // very bottom of the stack is aligned properly.
925 int partial_size
= frame_size
+ aux_data_size
;
926 int aligned_partial_size
= roundUp(partial_size
, align
);
927 int aux_padding
= aligned_partial_size
- partial_size
;
935 Addr stack_base
= memState
->getStackBase();
937 Addr stack_min
= stack_base
- space_needed
;
938 stack_min
= roundDown(stack_min
, align
);
940 unsigned stack_size
= stack_base
- stack_min
;
941 stack_size
= roundUp(stack_size
, pageSize
);
942 memState
->setStackSize(stack_size
);
945 Addr stack_end
= roundDown(stack_base
- stack_size
, pageSize
);
947 DPRINTF(Stack
, "Mapping the stack: 0x%x %dB\n", stack_end
, stack_size
);
948 allocateMem(stack_end
, stack_size
);
950 // map out initial stack contents
951 IntType sentry_base
= stack_base
- sentry_size
;
952 IntType file_name_base
= sentry_base
- file_name_size
;
953 IntType env_data_base
= file_name_base
- env_data_size
;
954 IntType arg_data_base
= env_data_base
- arg_data_size
;
955 IntType aux_data_base
= arg_data_base
- info_block_padding
- aux_data_size
;
956 IntType auxv_array_base
= aux_data_base
- aux_array_size
- aux_padding
;
957 IntType envp_array_base
= auxv_array_base
- envp_array_size
;
958 IntType argv_array_base
= envp_array_base
- argv_array_size
;
959 IntType argc_base
= argv_array_base
- argc_size
;
961 DPRINTF(Stack
, "The addresses of items on the initial stack:\n");
962 DPRINTF(Stack
, "0x%x - file name\n", file_name_base
);
963 DPRINTF(Stack
, "0x%x - env data\n", env_data_base
);
964 DPRINTF(Stack
, "0x%x - arg data\n", arg_data_base
);
965 DPRINTF(Stack
, "0x%x - aux data\n", aux_data_base
);
966 DPRINTF(Stack
, "0x%x - auxv array\n", auxv_array_base
);
967 DPRINTF(Stack
, "0x%x - envp array\n", envp_array_base
);
968 DPRINTF(Stack
, "0x%x - argv array\n", argv_array_base
);
969 DPRINTF(Stack
, "0x%x - argc \n", argc_base
);
970 DPRINTF(Stack
, "0x%x - stack min\n", stack_min
);
972 // write contents to stack
975 IntType argc
= argv
.size();
976 IntType guestArgc
= htole(argc
);
978 // Write out the sentry void *
979 IntType sentry_NULL
= 0;
980 initVirtMem
.writeBlob(sentry_base
, &sentry_NULL
, sentry_size
);
982 // Write the file name
983 initVirtMem
.writeString(file_name_base
, filename
.c_str());
985 // Fix up the aux vectors which point to data
986 assert(auxv
[auxv
.size() - 3].type
== M5_AT_RANDOM
);
987 auxv
[auxv
.size() - 3].val
= aux_data_base
;
988 assert(auxv
[auxv
.size() - 2].type
== M5_AT_EXECFN
);
989 auxv
[auxv
.size() - 2].val
= argv_array_base
;
990 assert(auxv
[auxv
.size() - 1].type
== M5_AT_PLATFORM
);
991 auxv
[auxv
.size() - 1].val
= aux_data_base
+ numRandomBytes
;
994 // Copy the aux stuff
995 Addr auxv_array_end
= auxv_array_base
;
996 for (const auto &aux
: auxv
) {
997 initVirtMem
.write(auxv_array_end
, aux
, GuestByteOrder
);
998 auxv_array_end
+= sizeof(aux
);
1000 // Write out the terminating zeroed auxiliary vector
1001 const AuxVector
<uint64_t> zero(0, 0);
1002 initVirtMem
.write(auxv_array_end
, zero
);
1003 auxv_array_end
+= sizeof(zero
);
1005 initVirtMem
.writeString(aux_data_base
, platform
.c_str());
1007 copyStringArray(envp
, envp_array_base
, env_data_base
,
1008 LittleEndianByteOrder
, initVirtMem
);
1009 copyStringArray(argv
, argv_array_base
, arg_data_base
,
1010 LittleEndianByteOrder
, initVirtMem
);
1012 initVirtMem
.writeBlob(argc_base
, &guestArgc
, intSize
);
1014 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
1015 // Set the stack pointer register
1016 tc
->setIntReg(StackPointerReg
, stack_min
);
1018 // There doesn't need to be any segment base added in since we're dealing
1019 // with the flat segmentation model.
1020 tc
->pcState(getStartPC());
1022 // Align the "stack_min" to a page boundary.
1023 memState
->setStackMin(roundDown(stack_min
, pageSize
));
1027 X86_64Process::argsInit(int pageSize
)
1029 std::vector
<AuxVector
<uint64_t> > extraAuxvs
;
1030 extraAuxvs
.emplace_back(M5_AT_SYSINFO_EHDR
, vsyscallPage
.base
);
1031 X86Process::argsInit
<uint64_t>(pageSize
, extraAuxvs
);
1035 I386Process::argsInit(int pageSize
)
1037 std::vector
<AuxVector
<uint32_t> > extraAuxvs
;
1038 //Tell the binary where the vsyscall part of the vsyscall page is.
1039 extraAuxvs
.emplace_back(M5_AT_SYSINFO
,
1040 vsyscallPage
.base
+ vsyscallPage
.vsyscallOffset
);
1041 extraAuxvs
.emplace_back(M5_AT_SYSINFO_EHDR
, vsyscallPage
.base
);
1042 X86Process::argsInit
<uint32_t>(pageSize
, extraAuxvs
);
1046 X86Process::setSyscallReturn(ThreadContext
*tc
, SyscallReturn retval
)
1048 tc
->setIntReg(INTREG_RAX
, retval
.encodedValue());
1052 X86_64Process::getSyscallArg(ThreadContext
*tc
, int &i
)
1054 assert(i
< NumArgumentRegs
);
1055 return tc
->readIntReg(ArgumentReg
[i
++]);
1059 X86_64Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1060 Process
*p
, RegVal flags
)
1062 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1063 ((X86_64Process
*)p
)->vsyscallPage
= vsyscallPage
;
1067 I386Process::getSyscallArg(ThreadContext
*tc
, int &i
)
1069 assert(i
< NumArgumentRegs32
);
1070 return tc
->readIntReg(ArgumentReg32
[i
++]);
1074 I386Process::getSyscallArg(ThreadContext
*tc
, int &i
, int width
)
1076 assert(width
== 32 || width
== 64);
1077 assert(i
< NumArgumentRegs
);
1078 uint64_t retVal
= tc
->readIntReg(ArgumentReg32
[i
++]) & mask(32);
1080 retVal
|= ((uint64_t)tc
->readIntReg(ArgumentReg
[i
++]) << 32);
1085 I386Process::clone(ThreadContext
*old_tc
, ThreadContext
*new_tc
,
1086 Process
*p
, RegVal flags
)
1088 X86Process::clone(old_tc
, new_tc
, p
, flags
);
1089 ((I386Process
*)p
)->vsyscallPage
= vsyscallPage
;