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40 #ifndef __ARCH_X86_REGISTERS_HH__
41 #define __ARCH_X86_REGISTERS_HH__
43 #include "arch/x86/generated/max_inst_regs.hh"
44 #include "arch/x86/regs/int.hh"
45 #include "arch/x86/regs/misc.hh"
46 #include "arch/x86/x86_traits.hh"
50 using X86ISAInst::MaxInstSrcRegs;
51 using X86ISAInst::MaxInstDestRegs;
52 const int NumMiscArchRegs = NUM_MISCREGS;
53 const int NumMiscRegs = NUM_MISCREGS;
55 const int NumIntArchRegs = NUM_INTREGS;
56 const int NumIntRegs =
57 NumIntArchRegs + NumMicroIntRegs +
58 NumPseudoIntRegs + NumImplicitIntRegs;
60 //Each 128 bit xmm register is broken into two effective 64 bit registers.
61 const int NumFloatRegs =
62 NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
63 const int NumFloatArchRegs = NumFloatRegs + 8;
65 // These enumerate all the registers for dependence tracking.
67 //There are 16 microcode registers at the moment. This is an
68 //unusually large constant to make sure there isn't overflow.
76 //The microcode fp registers
78 //The indices that are mapped over the fp stack
80 Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
83 // semantically meaningful register indices
84 //There is no such register in X86
85 const int ZeroReg = NUM_INTREGS;
86 const int StackPointerReg = INTREG_RSP;
87 //X86 doesn't seem to have a link register
88 const int ReturnAddressReg = 0;
89 const int ReturnValueReg = INTREG_RAX;
90 const int FramePointerReg = INTREG_RBP;
92 // Some OS syscalls use a second register (rdx) to return a second
94 const int SyscallPseudoReturnReg = INTREG_RDX;
96 typedef uint64_t IntReg;
97 //XXX Should this be a 128 bit structure for XMM memory ops?
98 typedef uint64_t LargestRead;
99 typedef uint64_t MiscReg;
101 //These floating point types are correct for mmx, but not
102 //technically for x87 (80 bits) or at all for xmm (128 bits)
103 typedef double FloatReg;
104 typedef uint64_t FloatRegBits;
112 typedef uint16_t RegIndex;
114 } // namespace X86ISA
116 #endif // __ARCH_X86_REGFILE_HH__