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58 #include "arch/x86/bios/smbios.hh"
59 #include "arch/x86/bios/intelmp.hh"
60 #include "arch/x86/miscregs.hh"
61 #include "arch/x86/system.hh"
62 #include "arch/vtophys.hh"
63 #include "base/intmath.hh"
64 #include "base/loader/object_file.hh"
65 #include "base/loader/symtab.hh"
66 #include "base/remote_gdb.hh"
67 #include "base/trace.hh"
68 #include "cpu/thread_context.hh"
69 #include "mem/physical.hh"
70 #include "params/X86System.hh"
71 #include "sim/byteswap.hh"
74 using namespace LittleEndianGuest
;
75 using namespace X86ISA
;
77 X86System::X86System(Params
*p
) :
78 System(p
), smbiosTable(p
->smbios_table
),
79 mpFloatingPointer(p
->intel_mp_pointer
),
80 mpConfigTable(p
->intel_mp_table
),
81 rsdp(p
->acpi_description_table_pointer
)
85 installSegDesc(ThreadContext
*tc
, SegmentRegIndex seg
,
86 SegDescriptor desc
, bool longmode
)
88 uint64_t base
= desc
.baseLow
+ (desc
.baseHigh
<< 24);
89 bool honorBase
= !longmode
|| seg
== SEGMENT_REG_FS
||
90 seg
== SEGMENT_REG_GS
||
91 seg
== SEGMENT_REG_TSL
||
92 seg
== SYS_SEGMENT_REG_TR
;
93 uint64_t limit
= desc
.limitLow
| (desc
.limitHigh
<< 16);
99 attr
.defaultSize
= desc
.d
;
100 attr
.longMode
= desc
.l
;
102 attr
.granularity
= desc
.g
;
103 attr
.present
= desc
.p
;
104 attr
.system
= desc
.s
;
105 attr
.type
= desc
.type
;
107 if (desc
.type
.codeOrData
) {
110 attr
.readable
= desc
.type
.r
;
114 attr
.expandDown
= desc
.type
.e
;
116 attr
.writable
= desc
.type
.w
;
124 tc
->setMiscReg(MISCREG_SEG_BASE(seg
), base
);
125 tc
->setMiscReg(MISCREG_SEG_EFF_BASE(seg
), honorBase
? base
: 0);
126 tc
->setMiscReg(MISCREG_SEG_LIMIT(seg
), limit
);
127 tc
->setMiscReg(MISCREG_SEG_ATTR(seg
), (MiscReg
)attr
);
134 ThreadContext
*tc
= threadContexts
[0];
135 // This is the boot strap processor (BSP). Initialize it to look like
136 // the boot loader has just turned control over to the 64 bit OS. We
137 // won't actually set up real mode or legacy protected mode descriptor
138 // tables because we aren't executing any code that would require
139 // them. We do, however toggle the control bits in the correct order
140 // while allowing consistency checks and the underlying mechansims
143 const int NumPDTs
= 4;
145 const Addr PageMapLevel4
= 0x70000;
146 const Addr PageDirPtrTable
= 0x71000;
147 const Addr PageDirTable
[NumPDTs
] =
148 {0x72000, 0x73000, 0x74000, 0x75000};
149 const Addr GDTBase
= 0x76000;
151 const int PML4Bits
= 9;
152 const int PDPTBits
= 9;
153 const int PDTBits
= 9;
155 // Get a port to write the page tables and descriptor tables.
156 FunctionalPort
* physPort
= tc
->getPhysPort();
161 uint8_t numGDTEntries
= 0;
162 // Place holder at selector 0
163 uint64_t nullDescriptor
= 0;
164 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
165 (uint8_t *)(&nullDescriptor
), 8);
168 //64 bit code segment
169 SegDescriptor csDesc
= 0;
170 csDesc
.type
.codeOrData
= 1;
171 csDesc
.type
.c
= 0; // Not conforming
172 csDesc
.type
.r
= 1; // Readable
173 csDesc
.dpl
= 0; // Privelege level 0
174 csDesc
.p
= 1; // Present
175 csDesc
.l
= 1; // 64 bit
176 csDesc
.d
= 0; // default operand size
177 csDesc
.g
= 1; // Page granularity
178 csDesc
.s
= 1; // Not a system segment
179 csDesc
.limitHigh
= 0xF;
180 csDesc
.limitLow
= 0xFF;
181 //Because we're dealing with a pointer and I don't think it's
182 //guaranteed that there isn't anything in a nonvirtual class between
183 //it's beginning in memory and it's actual data, we'll use an
185 uint64_t csDescVal
= csDesc
;
186 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
187 (uint8_t *)(&csDescVal
), 8);
192 cs
.si
= numGDTEntries
- 1;
194 tc
->setMiscReg(MISCREG_CS
, (MiscReg
)cs
);
196 //32 bit data segment
197 SegDescriptor dsDesc
= 0;
198 dsDesc
.type
.codeOrData
= 0;
199 dsDesc
.type
.e
= 0; // Not expand down
200 dsDesc
.type
.w
= 1; // Writable
201 dsDesc
.dpl
= 0; // Privelege level 0
202 dsDesc
.p
= 1; // Present
203 dsDesc
.d
= 1; // default operand size
204 dsDesc
.g
= 1; // Page granularity
205 dsDesc
.s
= 1; // Not a system segment
206 dsDesc
.limitHigh
= 0xF;
207 dsDesc
.limitLow
= 0xFF;
208 uint64_t dsDescVal
= dsDesc
;
209 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
210 (uint8_t *)(&dsDescVal
), 8);
215 ds
.si
= numGDTEntries
- 1;
217 tc
->setMiscReg(MISCREG_DS
, (MiscReg
)ds
);
218 tc
->setMiscReg(MISCREG_ES
, (MiscReg
)ds
);
219 tc
->setMiscReg(MISCREG_FS
, (MiscReg
)ds
);
220 tc
->setMiscReg(MISCREG_GS
, (MiscReg
)ds
);
221 tc
->setMiscReg(MISCREG_SS
, (MiscReg
)ds
);
223 tc
->setMiscReg(MISCREG_TSL
, 0);
224 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTBase
);
225 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 8 * numGDTEntries
- 1);
227 SegDescriptor tssDesc
= 0;
229 tssDesc
.dpl
= 0; // Privelege level 0
230 tssDesc
.p
= 1; // Present
231 tssDesc
.d
= 1; // default operand size
232 tssDesc
.g
= 1; // Page granularity
233 tssDesc
.s
= 1; // Not a system segment
234 tssDesc
.limitHigh
= 0xF;
235 tssDesc
.limitLow
= 0xFF;
236 uint64_t tssDescVal
= tssDesc
;
237 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
238 (uint8_t *)(&tssDescVal
), 8);
243 tss
.si
= numGDTEntries
- 1;
245 tc
->setMiscReg(MISCREG_TR
, (MiscReg
)tss
);
246 installSegDesc(tc
, SYS_SEGMENT_REG_TR
, tssDesc
, true);
249 * Identity map the first 4GB of memory. In order to map this region
250 * of memory in long mode, there needs to be one actual page map level
251 * 4 entry which points to one page directory pointer table which
252 * points to 4 different page directory tables which are full of two
253 * megabyte pages. All of the other entries in valid tables are set
254 * to indicate that they don't pertain to anything valid and will
255 * cause a fault if used.
258 // Put valid values in all of the various table entries which indicate
259 // that those entries don't point to further tables or pages. Then
260 // set the values of those entries which are needed.
264 // read/write, user, not present
265 uint64_t pml4e
= X86ISA::htog(0x6);
266 for (int offset
= 0; offset
< (1 << PML4Bits
) * 8; offset
+= 8) {
267 physPort
->writeBlob(PageMapLevel4
+ offset
, (uint8_t *)(&pml4e
), 8);
269 // Point to the only PDPT
270 pml4e
= X86ISA::htog(0x7 | PageDirPtrTable
);
271 physPort
->writeBlob(PageMapLevel4
, (uint8_t *)(&pml4e
), 8);
273 // Page Directory Pointer Table
275 // read/write, user, not present
276 uint64_t pdpe
= X86ISA::htog(0x6);
277 for (int offset
= 0; offset
< (1 << PDPTBits
) * 8; offset
+= 8) {
278 physPort
->writeBlob(PageDirPtrTable
+ offset
,
279 (uint8_t *)(&pdpe
), 8);
282 for (int table
= 0; table
< NumPDTs
; table
++) {
283 pdpe
= X86ISA::htog(0x7 | PageDirTable
[table
]);
284 physPort
->writeBlob(PageDirPtrTable
+ table
* 8,
285 (uint8_t *)(&pdpe
), 8);
288 // Page Directory Tables
291 const Addr pageSize
= 2 << 20;
292 for (int table
= 0; table
< NumPDTs
; table
++) {
293 for (int offset
= 0; offset
< (1 << PDTBits
) * 8; offset
+= 8) {
294 // read/write, user, present, 4MB
295 uint64_t pdte
= X86ISA::htog(0x87 | base
);
296 physPort
->writeBlob(PageDirTable
[table
] + offset
,
297 (uint8_t *)(&pdte
), 8);
303 * Transition from real mode all the way up to Long mode
305 CR0 cr0
= tc
->readMiscRegNoEffect(MISCREG_CR0
);
308 tc
->setMiscReg(MISCREG_CR0
, cr0
);
309 //Turn on protected mode.
311 tc
->setMiscReg(MISCREG_CR0
, cr0
);
313 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
316 tc
->setMiscReg(MISCREG_CR4
, cr4
);
318 //Point to the page tables.
319 tc
->setMiscReg(MISCREG_CR3
, PageMapLevel4
);
321 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
324 tc
->setMiscReg(MISCREG_EFER
, efer
);
326 //Start using longmode segments.
327 installSegDesc(tc
, SEGMENT_REG_CS
, csDesc
, true);
328 installSegDesc(tc
, SEGMENT_REG_DS
, dsDesc
, true);
329 installSegDesc(tc
, SEGMENT_REG_ES
, dsDesc
, true);
330 installSegDesc(tc
, SEGMENT_REG_FS
, dsDesc
, true);
331 installSegDesc(tc
, SEGMENT_REG_GS
, dsDesc
, true);
332 installSegDesc(tc
, SEGMENT_REG_SS
, dsDesc
, true);
334 //Activate long mode.
336 tc
->setMiscReg(MISCREG_CR0
, cr0
);
338 tc
->setPC(tc
->getSystemPtr()->kernelEntry
);
339 tc
->setNextPC(tc
->readPC());
341 // We should now be in long mode. Yay!
343 Addr ebdaPos
= 0xF0000;
346 //Write out the SMBios/DMI table
347 writeOutSMBiosTable(ebdaPos
, fixed
, table
);
348 ebdaPos
+= (fixed
+ table
);
349 ebdaPos
= roundUp(ebdaPos
, 16);
351 //Write out the Intel MP Specification configuration table
352 writeOutMPTable(ebdaPos
, fixed
, table
);
353 ebdaPos
+= (fixed
+ table
);
357 X86System::writeOutSMBiosTable(Addr header
,
358 Addr
&headerSize
, Addr
&structSize
, Addr table
)
360 // Get a port to write the table and header to memory.
361 FunctionalPort
* physPort
= threadContexts
[0]->getPhysPort();
363 // If the table location isn't specified, just put it after the header.
364 // The header size as of the 2.5 SMBios specification is 0x1F bytes
366 table
= header
+ 0x1F;
367 smbiosTable
->setTableAddr(table
);
369 smbiosTable
->writeOut(physPort
, header
, headerSize
, structSize
);
371 // Do some bounds checking to make sure we at least didn't step on
373 assert(header
> table
|| header
+ headerSize
<= table
);
374 assert(table
> header
|| table
+ structSize
<= header
);
378 X86System::writeOutMPTable(Addr fp
,
379 Addr
&fpSize
, Addr
&tableSize
, Addr table
)
381 // Get a port to write the table and header to memory.
382 FunctionalPort
* physPort
= threadContexts
[0]->getPhysPort();
384 // If the table location isn't specified and it exists, just put
385 // it after the floating pointer. The fp size as of the 1.4 Intel MP
386 // specification is 0x10 bytes.
390 mpFloatingPointer
->setTableAddr(table
);
393 fpSize
= mpFloatingPointer
->writeOut(physPort
, fp
);
395 tableSize
= mpConfigTable
->writeOut(physPort
, table
);
399 // Do some bounds checking to make sure we at least didn't step on
400 // ourselves and the fp structure was the size we thought it was.
401 assert(fp
> table
|| fp
+ fpSize
<= table
);
402 assert(table
> fp
|| table
+ tableSize
<= fp
);
403 assert(fpSize
== 0x10);
407 X86System::~X86System()
413 X86System::serialize(std::ostream
&os
)
415 System::serialize(os
);
420 X86System::unserialize(Checkpoint
*cp
, const std::string
§ion
)
422 System::unserialize(cp
,section
);
426 X86SystemParams::create()
428 return new X86System(this);