src/arch/x86/system.cc

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  */
  39
  40 #include "arch/x86/bios/intelmp.hh"
  41 #include "arch/x86/bios/smbios.hh"
  42 #include "arch/x86/regs/misc.hh"
  43 #include "arch/x86/isa_traits.hh"
  44 #include "arch/x86/system.hh"
  45 #include "arch/vtophys.hh"
  46 #include "base/loader/object_file.hh"
  47 #include "base/loader/symtab.hh"
  48 #include "base/intmath.hh"
  49 #include "base/trace.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "mem/port_proxy.hh"
  52 #include "params/X86System.hh"
  53 #include "sim/byteswap.hh"
  54
  55 using namespace LittleEndianGuest;
  56 using namespace X86ISA;
  57
  58 X86System::X86System(Params *p) :
  59     System(p), smbiosTable(p->smbios_table),
  60     mpFloatingPointer(p->intel_mp_pointer),
  61     mpConfigTable(p->intel_mp_table),
  62     rsdp(p->acpi_description_table_pointer)
  63 {
  64 }
  65
  66 static void
  67 installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
  68         SegDescriptor desc, bool longmode)
  69 {
  70     uint64_t base = desc.baseLow + (desc.baseHigh << 24);
  71     bool honorBase = !longmode || seg == SEGMENT_REG_FS ||
  72                                   seg == SEGMENT_REG_GS ||
  73                                   seg == SEGMENT_REG_TSL ||
  74                                   seg == SYS_SEGMENT_REG_TR;
  75     uint64_t limit = desc.limitLow | (desc.limitHigh << 16);
  76
  77     SegAttr attr = 0;
  78
  79     attr.dpl = desc.dpl;
  80     attr.unusable = 0;
  81     attr.defaultSize = desc.d;
  82     attr.longMode = desc.l;
  83     attr.avl = desc.avl;
  84     attr.granularity = desc.g;
  85     attr.present = desc.p;
  86     attr.system = desc.s;
  87     attr.type = desc.type;
  88     if (desc.s) {
  89         if (desc.type.codeOrData) {
  90             // Code segment
  91             attr.expandDown = 0;
  92             attr.readable = desc.type.r;
  93             attr.writable = 0;
  94         } else {
  95             // Data segment
  96             attr.expandDown = desc.type.e;
  97             attr.readable = 1;
  98             attr.writable = desc.type.w;
  99         }
 100     } else {
 101         attr.readable = 1;
 102         attr.writable = 1;
 103         attr.expandDown = 0;
 104     }
 105
 106     tc->setMiscReg(MISCREG_SEG_BASE(seg), base);
 107     tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? base : 0);
 108     tc->setMiscReg(MISCREG_SEG_LIMIT(seg), limit);
 109     tc->setMiscReg(MISCREG_SEG_ATTR(seg), (MiscReg)attr);
 110 }
 111
 112 void
 113 X86System::initState()
 114 {
 115     System::initState();
 116
 117     if (!kernel)
 118         fatal("No kernel to load.\n");
 119
 120     if (kernel->getArch() == ObjectFile::I386)
 121         fatal("Loading a 32 bit x86 kernel is not supported.\n");
 122
 123     ThreadContext *tc = threadContexts[0];
 124     // This is the boot strap processor (BSP). Initialize it to look like
 125     // the boot loader has just turned control over to the 64 bit OS. We
 126     // won't actually set up real mode or legacy protected mode descriptor
 127     // tables because we aren't executing any code that would require
 128     // them. We do, however toggle the control bits in the correct order
 129     // while allowing consistency checks and the underlying mechansims
 130     // just to be safe.
 131
 132     const int NumPDTs = 4;
 133
 134     const Addr PageMapLevel4 = 0x70000;
 135     const Addr PageDirPtrTable = 0x71000;
 136     const Addr PageDirTable[NumPDTs] =
 137         {0x72000, 0x73000, 0x74000, 0x75000};
 138     const Addr GDTBase = 0x76000;
 139
 140     const int PML4Bits = 9;
 141     const int PDPTBits = 9;
 142     const int PDTBits = 9;
 143
 144     /*
 145      * Set up the gdt.
 146      */
 147     uint8_t numGDTEntries = 0;
 148     // Place holder at selector 0
 149     uint64_t nullDescriptor = 0;
 150     physProxy.writeBlob(GDTBase + numGDTEntries * 8,
 151                         (uint8_t *)(&nullDescriptor), 8);
 152     numGDTEntries++;
 153
 154     //64 bit code segment
 155     SegDescriptor csDesc = 0;
 156     csDesc.type.codeOrData = 1;
 157     csDesc.type.c = 0; // Not conforming
 158     csDesc.type.r = 1; // Readable
 159     csDesc.dpl = 0; // Privelege level 0
 160     csDesc.p = 1; // Present
 161     csDesc.l = 1; // 64 bit
 162     csDesc.d = 0; // default operand size
 163     csDesc.g = 1; // Page granularity
 164     csDesc.s = 1; // Not a system segment
 165     csDesc.limitHigh = 0xF;
 166     csDesc.limitLow = 0xFFFF;
 167     //Because we're dealing with a pointer and I don't think it's
 168     //guaranteed that there isn't anything in a nonvirtual class between
 169     //it's beginning in memory and it's actual data, we'll use an
 170     //intermediary.
 171     uint64_t csDescVal = csDesc;
 172     physProxy.writeBlob(GDTBase + numGDTEntries * 8,
 173                         (uint8_t *)(&csDescVal), 8);
 174
 175     numGDTEntries++;
 176
 177     SegSelector cs = 0;
 178     cs.si = numGDTEntries - 1;
 179
 180     tc->setMiscReg(MISCREG_CS, (MiscReg)cs);
 181
 182     //32 bit data segment
 183     SegDescriptor dsDesc = 0;
 184     dsDesc.type.codeOrData = 0;
 185     dsDesc.type.e = 0; // Not expand down
 186     dsDesc.type.w = 1; // Writable
 187     dsDesc.dpl = 0; // Privelege level 0
 188     dsDesc.p = 1; // Present
 189     dsDesc.d = 1; // default operand size
 190     dsDesc.g = 1; // Page granularity
 191     dsDesc.s = 1; // Not a system segment
 192     dsDesc.limitHigh = 0xF;
 193     dsDesc.limitLow = 0xFFFF;
 194     uint64_t dsDescVal = dsDesc;
 195     physProxy.writeBlob(GDTBase + numGDTEntries * 8,
 196                         (uint8_t *)(&dsDescVal), 8);
 197
 198     numGDTEntries++;
 199
 200     SegSelector ds = 0;
 201     ds.si = numGDTEntries - 1;
 202
 203     tc->setMiscReg(MISCREG_DS, (MiscReg)ds);
 204     tc->setMiscReg(MISCREG_ES, (MiscReg)ds);
 205     tc->setMiscReg(MISCREG_FS, (MiscReg)ds);
 206     tc->setMiscReg(MISCREG_GS, (MiscReg)ds);
 207     tc->setMiscReg(MISCREG_SS, (MiscReg)ds);
 208
 209     tc->setMiscReg(MISCREG_TSL, 0);
 210     tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
 211     tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
 212
 213     SegDescriptor tssDesc = 0;
 214     tssDesc.type = 0xB;
 215     tssDesc.dpl = 0; // Privelege level 0
 216     tssDesc.p = 1; // Present
 217     tssDesc.d = 1; // default operand size
 218     tssDesc.g = 1; // Page granularity
 219     tssDesc.s = 0;
 220     tssDesc.limitHigh = 0xF;
 221     tssDesc.limitLow = 0xFFFF;
 222     uint64_t tssDescVal = tssDesc;
 223     physProxy.writeBlob(GDTBase + numGDTEntries * 8,
 224                         (uint8_t *)(&tssDescVal), 8);
 225
 226     numGDTEntries++;
 227
 228     SegSelector tss = 0;
 229     tss.si = numGDTEntries - 1;
 230
 231     tc->setMiscReg(MISCREG_TR, (MiscReg)tss);
 232     installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true);
 233
 234     /*
 235      * Identity map the first 4GB of memory. In order to map this region
 236      * of memory in long mode, there needs to be one actual page map level
 237      * 4 entry which points to one page directory pointer table which
 238      * points to 4 different page directory tables which are full of two
 239      * megabyte pages. All of the other entries in valid tables are set
 240      * to indicate that they don't pertain to anything valid and will
 241      * cause a fault if used.
 242      */
 243
 244     // Put valid values in all of the various table entries which indicate
 245     // that those entries don't point to further tables or pages. Then
 246     // set the values of those entries which are needed.
 247
 248     // Page Map Level 4
 249
 250     // read/write, user, not present
 251     uint64_t pml4e = X86ISA::htog(0x6);
 252     for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
 253         physProxy.writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
 254     }
 255     // Point to the only PDPT
 256     pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
 257     physProxy.writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
 258
 259     // Page Directory Pointer Table
 260
 261     // read/write, user, not present
 262     uint64_t pdpe = X86ISA::htog(0x6);
 263     for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
 264         physProxy.writeBlob(PageDirPtrTable + offset,
 265                             (uint8_t *)(&pdpe), 8);
 266     }
 267     // Point to the PDTs
 268     for (int table = 0; table < NumPDTs; table++) {
 269         pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
 270         physProxy.writeBlob(PageDirPtrTable + table * 8,
 271                             (uint8_t *)(&pdpe), 8);
 272     }
 273
 274     // Page Directory Tables
 275
 276     Addr base = 0;
 277     const Addr pageSize = 2 << 20;
 278     for (int table = 0; table < NumPDTs; table++) {
 279         for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
 280             // read/write, user, present, 4MB
 281             uint64_t pdte = X86ISA::htog(0x87 | base);
 282             physProxy.writeBlob(PageDirTable[table] + offset,
 283                                 (uint8_t *)(&pdte), 8);
 284             base += pageSize;
 285         }
 286     }
 287
 288     /*
 289      * Transition from real mode all the way up to Long mode
 290      */
 291     CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
 292     //Turn off paging.
 293     cr0.pg = 0;
 294     tc->setMiscReg(MISCREG_CR0, cr0);
 295     //Turn on protected mode.
 296     cr0.pe = 1;
 297     tc->setMiscReg(MISCREG_CR0, cr0);
 298
 299     CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
 300     //Turn on pae.
 301     cr4.pae = 1;
 302     tc->setMiscReg(MISCREG_CR4, cr4);
 303
 304     //Point to the page tables.
 305     tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
 306
 307     Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
 308     //Enable long mode.
 309     efer.lme = 1;
 310     tc->setMiscReg(MISCREG_EFER, efer);
 311
 312     //Start using longmode segments.
 313     installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
 314     installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
 315     installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
 316     installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
 317     installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
 318     installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
 319
 320     //Activate long mode.
 321     cr0.pg = 1;
 322     tc->setMiscReg(MISCREG_CR0, cr0);
 323
 324     tc->pcState(tc->getSystemPtr()->kernelEntry);
 325
 326     // We should now be in long mode. Yay!
 327
 328     Addr ebdaPos = 0xF0000;
 329     Addr fixed, table;
 330
 331     //Write out the SMBios/DMI table
 332     writeOutSMBiosTable(ebdaPos, fixed, table);
 333     ebdaPos += (fixed + table);
 334     ebdaPos = roundUp(ebdaPos, 16);
 335
 336     //Write out the Intel MP Specification configuration table
 337     writeOutMPTable(ebdaPos, fixed, table);
 338     ebdaPos += (fixed + table);
 339 }
 340
 341 void
 342 X86System::writeOutSMBiosTable(Addr header,
 343         Addr &headerSize, Addr &structSize, Addr table)
 344 {
 345     // If the table location isn't specified, just put it after the header.
 346     // The header size as of the 2.5 SMBios specification is 0x1F bytes
 347     if (!table)
 348         table = header + 0x1F;
 349     smbiosTable->setTableAddr(table);
 350
 351     smbiosTable->writeOut(physProxy, header, headerSize, structSize);
 352
 353     // Do some bounds checking to make sure we at least didn't step on
 354     // ourselves.
 355     assert(header > table || header + headerSize <= table);
 356     assert(table > header || table + structSize <= header);
 357 }
 358
 359 void
 360 X86System::writeOutMPTable(Addr fp,
 361         Addr &fpSize, Addr &tableSize, Addr table)
 362 {
 363     // If the table location isn't specified and it exists, just put
 364     // it after the floating pointer. The fp size as of the 1.4 Intel MP
 365     // specification is 0x10 bytes.
 366     if (mpConfigTable) {
 367         if (!table)
 368             table = fp + 0x10;
 369         mpFloatingPointer->setTableAddr(table);
 370     }
 371
 372     fpSize = mpFloatingPointer->writeOut(physProxy, fp);
 373     if (mpConfigTable)
 374         tableSize = mpConfigTable->writeOut(physProxy, table);
 375     else
 376         tableSize = 0;
 377
 378     // Do some bounds checking to make sure we at least didn't step on
 379     // ourselves and the fp structure was the size we thought it was.
 380     assert(fp > table || fp + fpSize <= table);
 381     assert(table > fp || table + tableSize <= fp);
 382     assert(fpSize == 0x10);
 383 }
 384
 385
 386 X86System::~X86System()
 387 {
 388     delete smbiosTable;
 389 }
 390
 391 X86System *
 392 X86SystemParams::create()
 393 {
 394     return new X86System(this);
 395 }