2 * Copyright (c) 2007 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
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21 * neither the name of the copyright holders nor the names of its
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23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/x86/bios/smbios.hh"
41 #include "arch/x86/bios/intelmp.hh"
42 #include "arch/x86/miscregs.hh"
43 #include "arch/x86/system.hh"
44 #include "arch/vtophys.hh"
45 #include "base/intmath.hh"
46 #include "base/loader/object_file.hh"
47 #include "base/loader/symtab.hh"
48 #include "base/remote_gdb.hh"
49 #include "base/trace.hh"
50 #include "cpu/thread_context.hh"
51 #include "mem/physical.hh"
52 #include "params/X86System.hh"
53 #include "sim/byteswap.hh"
56 using namespace LittleEndianGuest
;
57 using namespace X86ISA
;
59 X86System::X86System(Params
*p
) :
60 System(p
), smbiosTable(p
->smbios_table
),
61 mpFloatingPointer(p
->intel_mp_pointer
),
62 mpConfigTable(p
->intel_mp_table
),
63 rsdp(p
->acpi_description_table_pointer
)
67 installSegDesc(ThreadContext
*tc
, SegmentRegIndex seg
,
68 SegDescriptor desc
, bool longmode
)
70 uint64_t base
= desc
.baseLow
+ (desc
.baseHigh
<< 24);
71 bool honorBase
= !longmode
|| seg
== SEGMENT_REG_FS
||
72 seg
== SEGMENT_REG_GS
||
73 seg
== SEGMENT_REG_TSL
||
74 seg
== SYS_SEGMENT_REG_TR
;
75 uint64_t limit
= desc
.limitLow
| (desc
.limitHigh
<< 16);
81 attr
.defaultSize
= desc
.d
;
82 attr
.longMode
= desc
.l
;
84 attr
.granularity
= desc
.g
;
85 attr
.present
= desc
.p
;
87 attr
.type
= desc
.type
;
89 if (desc
.type
.codeOrData
) {
92 attr
.readable
= desc
.type
.r
;
96 attr
.expandDown
= desc
.type
.e
;
98 attr
.writable
= desc
.type
.w
;
106 tc
->setMiscReg(MISCREG_SEG_BASE(seg
), base
);
107 tc
->setMiscReg(MISCREG_SEG_EFF_BASE(seg
), honorBase
? base
: 0);
108 tc
->setMiscReg(MISCREG_SEG_LIMIT(seg
), limit
);
109 tc
->setMiscReg(MISCREG_SEG_ATTR(seg
), (MiscReg
)attr
);
116 ThreadContext
*tc
= threadContexts
[0];
117 // This is the boot strap processor (BSP). Initialize it to look like
118 // the boot loader has just turned control over to the 64 bit OS. We
119 // won't actually set up real mode or legacy protected mode descriptor
120 // tables because we aren't executing any code that would require
121 // them. We do, however toggle the control bits in the correct order
122 // while allowing consistency checks and the underlying mechansims
125 const int NumPDTs
= 4;
127 const Addr PageMapLevel4
= 0x70000;
128 const Addr PageDirPtrTable
= 0x71000;
129 const Addr PageDirTable
[NumPDTs
] =
130 {0x72000, 0x73000, 0x74000, 0x75000};
131 const Addr GDTBase
= 0x76000;
133 const int PML4Bits
= 9;
134 const int PDPTBits
= 9;
135 const int PDTBits
= 9;
137 // Get a port to write the page tables and descriptor tables.
138 FunctionalPort
* physPort
= tc
->getPhysPort();
143 uint8_t numGDTEntries
= 0;
144 // Place holder at selector 0
145 uint64_t nullDescriptor
= 0;
146 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
147 (uint8_t *)(&nullDescriptor
), 8);
150 //64 bit code segment
151 SegDescriptor csDesc
= 0;
152 csDesc
.type
.codeOrData
= 1;
153 csDesc
.type
.c
= 0; // Not conforming
154 csDesc
.type
.r
= 1; // Readable
155 csDesc
.dpl
= 0; // Privelege level 0
156 csDesc
.p
= 1; // Present
157 csDesc
.l
= 1; // 64 bit
158 csDesc
.d
= 0; // default operand size
159 csDesc
.g
= 1; // Page granularity
160 csDesc
.s
= 1; // Not a system segment
161 csDesc
.limitHigh
= 0xF;
162 csDesc
.limitLow
= 0xFF;
163 //Because we're dealing with a pointer and I don't think it's
164 //guaranteed that there isn't anything in a nonvirtual class between
165 //it's beginning in memory and it's actual data, we'll use an
167 uint64_t csDescVal
= csDesc
;
168 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
169 (uint8_t *)(&csDescVal
), 8);
174 cs
.si
= numGDTEntries
- 1;
176 tc
->setMiscReg(MISCREG_CS
, (MiscReg
)cs
);
178 //32 bit data segment
179 SegDescriptor dsDesc
= 0;
180 dsDesc
.type
.codeOrData
= 0;
181 dsDesc
.type
.e
= 0; // Not expand down
182 dsDesc
.type
.w
= 1; // Writable
183 dsDesc
.dpl
= 0; // Privelege level 0
184 dsDesc
.p
= 1; // Present
185 dsDesc
.d
= 1; // default operand size
186 dsDesc
.g
= 1; // Page granularity
187 dsDesc
.s
= 1; // Not a system segment
188 dsDesc
.limitHigh
= 0xF;
189 dsDesc
.limitLow
= 0xFF;
190 uint64_t dsDescVal
= dsDesc
;
191 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
192 (uint8_t *)(&dsDescVal
), 8);
197 ds
.si
= numGDTEntries
- 1;
199 tc
->setMiscReg(MISCREG_DS
, (MiscReg
)ds
);
200 tc
->setMiscReg(MISCREG_ES
, (MiscReg
)ds
);
201 tc
->setMiscReg(MISCREG_FS
, (MiscReg
)ds
);
202 tc
->setMiscReg(MISCREG_GS
, (MiscReg
)ds
);
203 tc
->setMiscReg(MISCREG_SS
, (MiscReg
)ds
);
205 tc
->setMiscReg(MISCREG_TSL
, 0);
206 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTBase
);
207 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 8 * numGDTEntries
- 1);
209 SegDescriptor tssDesc
= 0;
211 tssDesc
.dpl
= 0; // Privelege level 0
212 tssDesc
.p
= 1; // Present
213 tssDesc
.d
= 1; // default operand size
214 tssDesc
.g
= 1; // Page granularity
215 tssDesc
.s
= 1; // Not a system segment
216 tssDesc
.limitHigh
= 0xF;
217 tssDesc
.limitLow
= 0xFF;
218 uint64_t tssDescVal
= tssDesc
;
219 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
220 (uint8_t *)(&tssDescVal
), 8);
225 tss
.si
= numGDTEntries
- 1;
227 tc
->setMiscReg(MISCREG_TR
, (MiscReg
)tss
);
228 installSegDesc(tc
, SYS_SEGMENT_REG_TR
, tssDesc
, true);
231 * Identity map the first 4GB of memory. In order to map this region
232 * of memory in long mode, there needs to be one actual page map level
233 * 4 entry which points to one page directory pointer table which
234 * points to 4 different page directory tables which are full of two
235 * megabyte pages. All of the other entries in valid tables are set
236 * to indicate that they don't pertain to anything valid and will
237 * cause a fault if used.
240 // Put valid values in all of the various table entries which indicate
241 // that those entries don't point to further tables or pages. Then
242 // set the values of those entries which are needed.
246 // read/write, user, not present
247 uint64_t pml4e
= X86ISA::htog(0x6);
248 for (int offset
= 0; offset
< (1 << PML4Bits
) * 8; offset
+= 8) {
249 physPort
->writeBlob(PageMapLevel4
+ offset
, (uint8_t *)(&pml4e
), 8);
251 // Point to the only PDPT
252 pml4e
= X86ISA::htog(0x7 | PageDirPtrTable
);
253 physPort
->writeBlob(PageMapLevel4
, (uint8_t *)(&pml4e
), 8);
255 // Page Directory Pointer Table
257 // read/write, user, not present
258 uint64_t pdpe
= X86ISA::htog(0x6);
259 for (int offset
= 0; offset
< (1 << PDPTBits
) * 8; offset
+= 8) {
260 physPort
->writeBlob(PageDirPtrTable
+ offset
,
261 (uint8_t *)(&pdpe
), 8);
264 for (int table
= 0; table
< NumPDTs
; table
++) {
265 pdpe
= X86ISA::htog(0x7 | PageDirTable
[table
]);
266 physPort
->writeBlob(PageDirPtrTable
+ table
* 8,
267 (uint8_t *)(&pdpe
), 8);
270 // Page Directory Tables
273 const Addr pageSize
= 2 << 20;
274 for (int table
= 0; table
< NumPDTs
; table
++) {
275 for (int offset
= 0; offset
< (1 << PDTBits
) * 8; offset
+= 8) {
276 // read/write, user, present, 4MB
277 uint64_t pdte
= X86ISA::htog(0x87 | base
);
278 physPort
->writeBlob(PageDirTable
[table
] + offset
,
279 (uint8_t *)(&pdte
), 8);
285 * Transition from real mode all the way up to Long mode
287 CR0 cr0
= tc
->readMiscRegNoEffect(MISCREG_CR0
);
290 tc
->setMiscReg(MISCREG_CR0
, cr0
);
291 //Turn on protected mode.
293 tc
->setMiscReg(MISCREG_CR0
, cr0
);
295 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
298 tc
->setMiscReg(MISCREG_CR4
, cr4
);
300 //Point to the page tables.
301 tc
->setMiscReg(MISCREG_CR3
, PageMapLevel4
);
303 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
306 tc
->setMiscReg(MISCREG_EFER
, efer
);
308 //Start using longmode segments.
309 installSegDesc(tc
, SEGMENT_REG_CS
, csDesc
, true);
310 installSegDesc(tc
, SEGMENT_REG_DS
, dsDesc
, true);
311 installSegDesc(tc
, SEGMENT_REG_ES
, dsDesc
, true);
312 installSegDesc(tc
, SEGMENT_REG_FS
, dsDesc
, true);
313 installSegDesc(tc
, SEGMENT_REG_GS
, dsDesc
, true);
314 installSegDesc(tc
, SEGMENT_REG_SS
, dsDesc
, true);
316 //Activate long mode.
318 tc
->setMiscReg(MISCREG_CR0
, cr0
);
320 tc
->setPC(tc
->getSystemPtr()->kernelEntry
);
321 tc
->setNextPC(tc
->readPC());
323 // We should now be in long mode. Yay!
325 Addr ebdaPos
= 0xF0000;
328 //Write out the SMBios/DMI table
329 writeOutSMBiosTable(ebdaPos
, fixed
, table
);
330 ebdaPos
+= (fixed
+ table
);
331 ebdaPos
= roundUp(ebdaPos
, 16);
333 //Write out the Intel MP Specification configuration table
334 writeOutMPTable(ebdaPos
, fixed
, table
);
335 ebdaPos
+= (fixed
+ table
);
339 X86System::writeOutSMBiosTable(Addr header
,
340 Addr
&headerSize
, Addr
&structSize
, Addr table
)
342 // Get a port to write the table and header to memory.
343 FunctionalPort
* physPort
= threadContexts
[0]->getPhysPort();
345 // If the table location isn't specified, just put it after the header.
346 // The header size as of the 2.5 SMBios specification is 0x1F bytes
348 table
= header
+ 0x1F;
349 smbiosTable
->setTableAddr(table
);
351 smbiosTable
->writeOut(physPort
, header
, headerSize
, structSize
);
353 // Do some bounds checking to make sure we at least didn't step on
355 assert(header
> table
|| header
+ headerSize
<= table
);
356 assert(table
> header
|| table
+ structSize
<= header
);
360 X86System::writeOutMPTable(Addr fp
,
361 Addr
&fpSize
, Addr
&tableSize
, Addr table
)
363 // Get a port to write the table and header to memory.
364 FunctionalPort
* physPort
= threadContexts
[0]->getPhysPort();
366 // If the table location isn't specified and it exists, just put
367 // it after the floating pointer. The fp size as of the 1.4 Intel MP
368 // specification is 0x10 bytes.
372 mpFloatingPointer
->setTableAddr(table
);
375 fpSize
= mpFloatingPointer
->writeOut(physPort
, fp
);
377 tableSize
= mpConfigTable
->writeOut(physPort
, table
);
381 // Do some bounds checking to make sure we at least didn't step on
382 // ourselves and the fp structure was the size we thought it was.
383 assert(fp
> table
|| fp
+ fpSize
<= table
);
384 assert(table
> fp
|| table
+ tableSize
<= fp
);
385 assert(fpSize
== 0x10);
389 X86System::~X86System()
395 X86System::serialize(std::ostream
&os
)
397 System::serialize(os
);
402 X86System::unserialize(Checkpoint
*cp
, const std::string
§ion
)
404 System::unserialize(cp
,section
);
408 X86SystemParams::create()
410 return new X86System(this);