2 * Copyright (c) 2007 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
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21 * neither the name of the copyright holders nor the names of its
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23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/x86/bios/smbios.hh"
41 #include "arch/x86/bios/intelmp.hh"
42 #include "arch/x86/regs/misc.hh"
43 #include "arch/x86/system.hh"
44 #include "arch/vtophys.hh"
45 #include "base/intmath.hh"
46 #include "base/loader/object_file.hh"
47 #include "base/loader/symtab.hh"
48 #include "base/trace.hh"
49 #include "cpu/thread_context.hh"
50 #include "mem/physical.hh"
51 #include "params/X86System.hh"
52 #include "sim/byteswap.hh"
55 using namespace LittleEndianGuest
;
56 using namespace X86ISA
;
58 X86System::X86System(Params
*p
) :
59 System(p
), smbiosTable(p
->smbios_table
),
60 mpFloatingPointer(p
->intel_mp_pointer
),
61 mpConfigTable(p
->intel_mp_table
),
62 rsdp(p
->acpi_description_table_pointer
)
64 if (kernel
->getArch() == ObjectFile::I386
)
65 fatal("Loading a 32 bit x86 kernel is not supported.\n");
69 installSegDesc(ThreadContext
*tc
, SegmentRegIndex seg
,
70 SegDescriptor desc
, bool longmode
)
72 uint64_t base
= desc
.baseLow
+ (desc
.baseHigh
<< 24);
73 bool honorBase
= !longmode
|| seg
== SEGMENT_REG_FS
||
74 seg
== SEGMENT_REG_GS
||
75 seg
== SEGMENT_REG_TSL
||
76 seg
== SYS_SEGMENT_REG_TR
;
77 uint64_t limit
= desc
.limitLow
| (desc
.limitHigh
<< 16);
83 attr
.defaultSize
= desc
.d
;
84 attr
.longMode
= desc
.l
;
86 attr
.granularity
= desc
.g
;
87 attr
.present
= desc
.p
;
89 attr
.type
= desc
.type
;
91 if (desc
.type
.codeOrData
) {
94 attr
.readable
= desc
.type
.r
;
98 attr
.expandDown
= desc
.type
.e
;
100 attr
.writable
= desc
.type
.w
;
108 tc
->setMiscReg(MISCREG_SEG_BASE(seg
), base
);
109 tc
->setMiscReg(MISCREG_SEG_EFF_BASE(seg
), honorBase
? base
: 0);
110 tc
->setMiscReg(MISCREG_SEG_LIMIT(seg
), limit
);
111 tc
->setMiscReg(MISCREG_SEG_ATTR(seg
), (MiscReg
)attr
);
115 X86System::initState()
119 ThreadContext
*tc
= threadContexts
[0];
120 // This is the boot strap processor (BSP). Initialize it to look like
121 // the boot loader has just turned control over to the 64 bit OS. We
122 // won't actually set up real mode or legacy protected mode descriptor
123 // tables because we aren't executing any code that would require
124 // them. We do, however toggle the control bits in the correct order
125 // while allowing consistency checks and the underlying mechansims
128 const int NumPDTs
= 4;
130 const Addr PageMapLevel4
= 0x70000;
131 const Addr PageDirPtrTable
= 0x71000;
132 const Addr PageDirTable
[NumPDTs
] =
133 {0x72000, 0x73000, 0x74000, 0x75000};
134 const Addr GDTBase
= 0x76000;
136 const int PML4Bits
= 9;
137 const int PDPTBits
= 9;
138 const int PDTBits
= 9;
140 // Get a port to write the page tables and descriptor tables.
141 FunctionalPort
* physPort
= tc
->getPhysPort();
146 uint8_t numGDTEntries
= 0;
147 // Place holder at selector 0
148 uint64_t nullDescriptor
= 0;
149 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
150 (uint8_t *)(&nullDescriptor
), 8);
153 //64 bit code segment
154 SegDescriptor csDesc
= 0;
155 csDesc
.type
.codeOrData
= 1;
156 csDesc
.type
.c
= 0; // Not conforming
157 csDesc
.type
.r
= 1; // Readable
158 csDesc
.dpl
= 0; // Privelege level 0
159 csDesc
.p
= 1; // Present
160 csDesc
.l
= 1; // 64 bit
161 csDesc
.d
= 0; // default operand size
162 csDesc
.g
= 1; // Page granularity
163 csDesc
.s
= 1; // Not a system segment
164 csDesc
.limitHigh
= 0xF;
165 csDesc
.limitLow
= 0xFF;
166 //Because we're dealing with a pointer and I don't think it's
167 //guaranteed that there isn't anything in a nonvirtual class between
168 //it's beginning in memory and it's actual data, we'll use an
170 uint64_t csDescVal
= csDesc
;
171 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
172 (uint8_t *)(&csDescVal
), 8);
177 cs
.si
= numGDTEntries
- 1;
179 tc
->setMiscReg(MISCREG_CS
, (MiscReg
)cs
);
181 //32 bit data segment
182 SegDescriptor dsDesc
= 0;
183 dsDesc
.type
.codeOrData
= 0;
184 dsDesc
.type
.e
= 0; // Not expand down
185 dsDesc
.type
.w
= 1; // Writable
186 dsDesc
.dpl
= 0; // Privelege level 0
187 dsDesc
.p
= 1; // Present
188 dsDesc
.d
= 1; // default operand size
189 dsDesc
.g
= 1; // Page granularity
190 dsDesc
.s
= 1; // Not a system segment
191 dsDesc
.limitHigh
= 0xF;
192 dsDesc
.limitLow
= 0xFF;
193 uint64_t dsDescVal
= dsDesc
;
194 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
195 (uint8_t *)(&dsDescVal
), 8);
200 ds
.si
= numGDTEntries
- 1;
202 tc
->setMiscReg(MISCREG_DS
, (MiscReg
)ds
);
203 tc
->setMiscReg(MISCREG_ES
, (MiscReg
)ds
);
204 tc
->setMiscReg(MISCREG_FS
, (MiscReg
)ds
);
205 tc
->setMiscReg(MISCREG_GS
, (MiscReg
)ds
);
206 tc
->setMiscReg(MISCREG_SS
, (MiscReg
)ds
);
208 tc
->setMiscReg(MISCREG_TSL
, 0);
209 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTBase
);
210 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 8 * numGDTEntries
- 1);
212 SegDescriptor tssDesc
= 0;
214 tssDesc
.dpl
= 0; // Privelege level 0
215 tssDesc
.p
= 1; // Present
216 tssDesc
.d
= 1; // default operand size
217 tssDesc
.g
= 1; // Page granularity
218 tssDesc
.s
= 1; // Not a system segment
219 tssDesc
.limitHigh
= 0xF;
220 tssDesc
.limitLow
= 0xFF;
221 uint64_t tssDescVal
= tssDesc
;
222 physPort
->writeBlob(GDTBase
+ numGDTEntries
* 8,
223 (uint8_t *)(&tssDescVal
), 8);
228 tss
.si
= numGDTEntries
- 1;
230 tc
->setMiscReg(MISCREG_TR
, (MiscReg
)tss
);
231 installSegDesc(tc
, SYS_SEGMENT_REG_TR
, tssDesc
, true);
234 * Identity map the first 4GB of memory. In order to map this region
235 * of memory in long mode, there needs to be one actual page map level
236 * 4 entry which points to one page directory pointer table which
237 * points to 4 different page directory tables which are full of two
238 * megabyte pages. All of the other entries in valid tables are set
239 * to indicate that they don't pertain to anything valid and will
240 * cause a fault if used.
243 // Put valid values in all of the various table entries which indicate
244 // that those entries don't point to further tables or pages. Then
245 // set the values of those entries which are needed.
249 // read/write, user, not present
250 uint64_t pml4e
= X86ISA::htog(0x6);
251 for (int offset
= 0; offset
< (1 << PML4Bits
) * 8; offset
+= 8) {
252 physPort
->writeBlob(PageMapLevel4
+ offset
, (uint8_t *)(&pml4e
), 8);
254 // Point to the only PDPT
255 pml4e
= X86ISA::htog(0x7 | PageDirPtrTable
);
256 physPort
->writeBlob(PageMapLevel4
, (uint8_t *)(&pml4e
), 8);
258 // Page Directory Pointer Table
260 // read/write, user, not present
261 uint64_t pdpe
= X86ISA::htog(0x6);
262 for (int offset
= 0; offset
< (1 << PDPTBits
) * 8; offset
+= 8) {
263 physPort
->writeBlob(PageDirPtrTable
+ offset
,
264 (uint8_t *)(&pdpe
), 8);
267 for (int table
= 0; table
< NumPDTs
; table
++) {
268 pdpe
= X86ISA::htog(0x7 | PageDirTable
[table
]);
269 physPort
->writeBlob(PageDirPtrTable
+ table
* 8,
270 (uint8_t *)(&pdpe
), 8);
273 // Page Directory Tables
276 const Addr pageSize
= 2 << 20;
277 for (int table
= 0; table
< NumPDTs
; table
++) {
278 for (int offset
= 0; offset
< (1 << PDTBits
) * 8; offset
+= 8) {
279 // read/write, user, present, 4MB
280 uint64_t pdte
= X86ISA::htog(0x87 | base
);
281 physPort
->writeBlob(PageDirTable
[table
] + offset
,
282 (uint8_t *)(&pdte
), 8);
288 * Transition from real mode all the way up to Long mode
290 CR0 cr0
= tc
->readMiscRegNoEffect(MISCREG_CR0
);
293 tc
->setMiscReg(MISCREG_CR0
, cr0
);
294 //Turn on protected mode.
296 tc
->setMiscReg(MISCREG_CR0
, cr0
);
298 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
301 tc
->setMiscReg(MISCREG_CR4
, cr4
);
303 //Point to the page tables.
304 tc
->setMiscReg(MISCREG_CR3
, PageMapLevel4
);
306 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
309 tc
->setMiscReg(MISCREG_EFER
, efer
);
311 //Start using longmode segments.
312 installSegDesc(tc
, SEGMENT_REG_CS
, csDesc
, true);
313 installSegDesc(tc
, SEGMENT_REG_DS
, dsDesc
, true);
314 installSegDesc(tc
, SEGMENT_REG_ES
, dsDesc
, true);
315 installSegDesc(tc
, SEGMENT_REG_FS
, dsDesc
, true);
316 installSegDesc(tc
, SEGMENT_REG_GS
, dsDesc
, true);
317 installSegDesc(tc
, SEGMENT_REG_SS
, dsDesc
, true);
319 //Activate long mode.
321 tc
->setMiscReg(MISCREG_CR0
, cr0
);
323 tc
->setPC(tc
->getSystemPtr()->kernelEntry
);
324 tc
->setNextPC(tc
->readPC());
326 // We should now be in long mode. Yay!
328 Addr ebdaPos
= 0xF0000;
331 //Write out the SMBios/DMI table
332 writeOutSMBiosTable(ebdaPos
, fixed
, table
);
333 ebdaPos
+= (fixed
+ table
);
334 ebdaPos
= roundUp(ebdaPos
, 16);
336 //Write out the Intel MP Specification configuration table
337 writeOutMPTable(ebdaPos
, fixed
, table
);
338 ebdaPos
+= (fixed
+ table
);
342 X86System::writeOutSMBiosTable(Addr header
,
343 Addr
&headerSize
, Addr
&structSize
, Addr table
)
345 // Get a port to write the table and header to memory.
346 FunctionalPort
* physPort
= threadContexts
[0]->getPhysPort();
348 // If the table location isn't specified, just put it after the header.
349 // The header size as of the 2.5 SMBios specification is 0x1F bytes
351 table
= header
+ 0x1F;
352 smbiosTable
->setTableAddr(table
);
354 smbiosTable
->writeOut(physPort
, header
, headerSize
, structSize
);
356 // Do some bounds checking to make sure we at least didn't step on
358 assert(header
> table
|| header
+ headerSize
<= table
);
359 assert(table
> header
|| table
+ structSize
<= header
);
363 X86System::writeOutMPTable(Addr fp
,
364 Addr
&fpSize
, Addr
&tableSize
, Addr table
)
366 // Get a port to write the table and header to memory.
367 FunctionalPort
* physPort
= threadContexts
[0]->getPhysPort();
369 // If the table location isn't specified and it exists, just put
370 // it after the floating pointer. The fp size as of the 1.4 Intel MP
371 // specification is 0x10 bytes.
375 mpFloatingPointer
->setTableAddr(table
);
378 fpSize
= mpFloatingPointer
->writeOut(physPort
, fp
);
380 tableSize
= mpConfigTable
->writeOut(physPort
, table
);
384 // Do some bounds checking to make sure we at least didn't step on
385 // ourselves and the fp structure was the size we thought it was.
386 assert(fp
> table
|| fp
+ fpSize
<= table
);
387 assert(table
> fp
|| table
+ tableSize
<= fp
);
388 assert(fpSize
== 0x10);
392 X86System::~X86System()
398 X86System::serialize(std::ostream
&os
)
400 System::serialize(os
);
405 X86System::unserialize(Checkpoint
*cp
, const std::string
§ion
)
407 System::unserialize(cp
,section
);
411 X86SystemParams::create()
413 return new X86System(this);