2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2018 TU Dresden
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
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13 * modified or unmodified, in source code or in binary form.
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18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
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24 * this software without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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42 #include "arch/x86/system.hh"
44 #include "arch/x86/bios/intelmp.hh"
45 #include "arch/x86/bios/smbios.hh"
46 #include "arch/x86/isa_traits.hh"
47 #include "base/loader/object_file.hh"
48 #include "cpu/thread_context.hh"
49 #include "params/X86System.hh"
51 using namespace LittleEndianGuest
;
52 using namespace X86ISA
;
54 X86System::X86System(Params
*p
) :
55 System(p
), smbiosTable(p
->smbios_table
),
56 mpFloatingPointer(p
->intel_mp_pointer
),
57 mpConfigTable(p
->intel_mp_table
),
58 rsdp(p
->acpi_description_table_pointer
)
63 X86ISA::installSegDesc(ThreadContext
*tc
, SegmentRegIndex seg
,
64 SegDescriptor desc
, bool longmode
)
66 bool honorBase
= !longmode
|| seg
== SEGMENT_REG_FS
||
67 seg
== SEGMENT_REG_GS
||
68 seg
== SEGMENT_REG_TSL
||
69 seg
== SYS_SEGMENT_REG_TR
;
75 attr
.defaultSize
= desc
.d
;
76 attr
.longMode
= desc
.l
;
78 attr
.granularity
= desc
.g
;
79 attr
.present
= desc
.p
;
81 attr
.type
= desc
.type
;
83 if (desc
.type
.codeOrData
) {
86 attr
.readable
= desc
.type
.r
;
90 attr
.expandDown
= desc
.type
.e
;
92 attr
.writable
= desc
.type
.w
;
100 tc
->setMiscReg(MISCREG_SEG_BASE(seg
), desc
.base
);
101 tc
->setMiscReg(MISCREG_SEG_EFF_BASE(seg
), honorBase
? desc
.base
: 0);
102 tc
->setMiscReg(MISCREG_SEG_LIMIT(seg
), desc
.limit
);
103 tc
->setMiscReg(MISCREG_SEG_ATTR(seg
), (RegVal
)attr
);
107 X86System::initState()
112 fatal("No kernel to load.\n");
114 if (kernel
->getArch() == ObjectFile::I386
)
115 fatal("Loading a 32 bit x86 kernel is not supported.\n");
117 ThreadContext
*tc
= threadContexts
[0];
118 // This is the boot strap processor (BSP). Initialize it to look like
119 // the boot loader has just turned control over to the 64 bit OS. We
120 // won't actually set up real mode or legacy protected mode descriptor
121 // tables because we aren't executing any code that would require
122 // them. We do, however toggle the control bits in the correct order
123 // while allowing consistency checks and the underlying mechansims
126 const int NumPDTs
= 4;
128 const Addr PageMapLevel4
= 0x70000;
129 const Addr PageDirPtrTable
= 0x71000;
130 const Addr PageDirTable
[NumPDTs
] =
131 {0x72000, 0x73000, 0x74000, 0x75000};
132 const Addr GDTBase
= 0x76000;
134 const int PML4Bits
= 9;
135 const int PDPTBits
= 9;
136 const int PDTBits
= 9;
141 uint8_t numGDTEntries
= 0;
142 // Place holder at selector 0
143 uint64_t nullDescriptor
= 0;
144 physProxy
.writeBlob(GDTBase
+ numGDTEntries
* 8, &nullDescriptor
, 8);
147 SegDescriptor initDesc
= 0;
148 initDesc
.type
.codeOrData
= 0; // code or data type
149 initDesc
.type
.c
= 0; // conforming
150 initDesc
.type
.r
= 1; // readable
151 initDesc
.dpl
= 0; // privilege
152 initDesc
.p
= 1; // present
153 initDesc
.l
= 1; // longmode - 64 bit
154 initDesc
.d
= 0; // operand size
155 initDesc
.g
= 1; // granularity
156 initDesc
.s
= 1; // system segment
157 initDesc
.limit
= 0xFFFFFFFF;
160 // 64 bit code segment
161 SegDescriptor csDesc
= initDesc
;
162 csDesc
.type
.codeOrData
= 1;
164 // Because we're dealing with a pointer and I don't think it's
165 // guaranteed that there isn't anything in a nonvirtual class between
166 // it's beginning in memory and it's actual data, we'll use an
168 uint64_t csDescVal
= csDesc
;
169 physProxy
.writeBlob(GDTBase
+ numGDTEntries
* 8, (&csDescVal
), 8);
174 cs
.si
= numGDTEntries
- 1;
176 tc
->setMiscReg(MISCREG_CS
, (RegVal
)cs
);
178 // 32 bit data segment
179 SegDescriptor dsDesc
= initDesc
;
180 uint64_t dsDescVal
= dsDesc
;
181 physProxy
.writeBlob(GDTBase
+ numGDTEntries
* 8, (&dsDescVal
), 8);
186 ds
.si
= numGDTEntries
- 1;
188 tc
->setMiscReg(MISCREG_DS
, (RegVal
)ds
);
189 tc
->setMiscReg(MISCREG_ES
, (RegVal
)ds
);
190 tc
->setMiscReg(MISCREG_FS
, (RegVal
)ds
);
191 tc
->setMiscReg(MISCREG_GS
, (RegVal
)ds
);
192 tc
->setMiscReg(MISCREG_SS
, (RegVal
)ds
);
194 tc
->setMiscReg(MISCREG_TSL
, 0);
195 tc
->setMiscReg(MISCREG_TSG_BASE
, GDTBase
);
196 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 8 * numGDTEntries
- 1);
198 SegDescriptor tssDesc
= initDesc
;
199 uint64_t tssDescVal
= tssDesc
;
200 physProxy
.writeBlob(GDTBase
+ numGDTEntries
* 8, (&tssDescVal
), 8);
205 tss
.si
= numGDTEntries
- 1;
207 tc
->setMiscReg(MISCREG_TR
, (RegVal
)tss
);
208 installSegDesc(tc
, SYS_SEGMENT_REG_TR
, tssDesc
, true);
211 * Identity map the first 4GB of memory. In order to map this region
212 * of memory in long mode, there needs to be one actual page map level
213 * 4 entry which points to one page directory pointer table which
214 * points to 4 different page directory tables which are full of two
215 * megabyte pages. All of the other entries in valid tables are set
216 * to indicate that they don't pertain to anything valid and will
217 * cause a fault if used.
220 // Put valid values in all of the various table entries which indicate
221 // that those entries don't point to further tables or pages. Then
222 // set the values of those entries which are needed.
226 // read/write, user, not present
227 uint64_t pml4e
= X86ISA::htog(0x6);
228 for (int offset
= 0; offset
< (1 << PML4Bits
) * 8; offset
+= 8) {
229 physProxy
.writeBlob(PageMapLevel4
+ offset
, (&pml4e
), 8);
231 // Point to the only PDPT
232 pml4e
= X86ISA::htog(0x7 | PageDirPtrTable
);
233 physProxy
.writeBlob(PageMapLevel4
, (&pml4e
), 8);
235 // Page Directory Pointer Table
237 // read/write, user, not present
238 uint64_t pdpe
= X86ISA::htog(0x6);
239 for (int offset
= 0; offset
< (1 << PDPTBits
) * 8; offset
+= 8)
240 physProxy
.writeBlob(PageDirPtrTable
+ offset
, &pdpe
, 8);
242 for (int table
= 0; table
< NumPDTs
; table
++) {
243 pdpe
= X86ISA::htog(0x7 | PageDirTable
[table
]);
244 physProxy
.writeBlob(PageDirPtrTable
+ table
* 8, &pdpe
, 8);
247 // Page Directory Tables
250 const Addr pageSize
= 2 << 20;
251 for (int table
= 0; table
< NumPDTs
; table
++) {
252 for (int offset
= 0; offset
< (1 << PDTBits
) * 8; offset
+= 8) {
253 // read/write, user, present, 4MB
254 uint64_t pdte
= X86ISA::htog(0x87 | base
);
255 physProxy
.writeBlob(PageDirTable
[table
] + offset
, &pdte
, 8);
261 * Transition from real mode all the way up to Long mode
263 CR0 cr0
= tc
->readMiscRegNoEffect(MISCREG_CR0
);
266 tc
->setMiscReg(MISCREG_CR0
, cr0
);
267 // Turn on protected mode.
269 tc
->setMiscReg(MISCREG_CR0
, cr0
);
271 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
274 tc
->setMiscReg(MISCREG_CR4
, cr4
);
276 // Point to the page tables.
277 tc
->setMiscReg(MISCREG_CR3
, PageMapLevel4
);
279 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
282 tc
->setMiscReg(MISCREG_EFER
, efer
);
284 // Start using longmode segments.
285 installSegDesc(tc
, SEGMENT_REG_CS
, csDesc
, true);
286 installSegDesc(tc
, SEGMENT_REG_DS
, dsDesc
, true);
287 installSegDesc(tc
, SEGMENT_REG_ES
, dsDesc
, true);
288 installSegDesc(tc
, SEGMENT_REG_FS
, dsDesc
, true);
289 installSegDesc(tc
, SEGMENT_REG_GS
, dsDesc
, true);
290 installSegDesc(tc
, SEGMENT_REG_SS
, dsDesc
, true);
292 // Activate long mode.
294 tc
->setMiscReg(MISCREG_CR0
, cr0
);
296 tc
->pcState(tc
->getSystemPtr()->kernelEntry
);
298 // We should now be in long mode. Yay!
300 Addr ebdaPos
= 0xF0000;
303 // Write out the SMBios/DMI table.
304 writeOutSMBiosTable(ebdaPos
, fixed
, table
);
305 ebdaPos
+= (fixed
+ table
);
306 ebdaPos
= roundUp(ebdaPos
, 16);
308 // Write out the Intel MP Specification configuration table.
309 writeOutMPTable(ebdaPos
, fixed
, table
);
310 ebdaPos
+= (fixed
+ table
);
314 X86System::writeOutSMBiosTable(Addr header
,
315 Addr
&headerSize
, Addr
&structSize
, Addr table
)
317 // If the table location isn't specified, just put it after the header.
318 // The header size as of the 2.5 SMBios specification is 0x1F bytes.
320 table
= header
+ 0x1F;
321 smbiosTable
->setTableAddr(table
);
323 smbiosTable
->writeOut(physProxy
, header
, headerSize
, structSize
);
325 // Do some bounds checking to make sure we at least didn't step on
327 assert(header
> table
|| header
+ headerSize
<= table
);
328 assert(table
> header
|| table
+ structSize
<= header
);
332 X86System::writeOutMPTable(Addr fp
,
333 Addr
&fpSize
, Addr
&tableSize
, Addr table
)
335 // If the table location isn't specified and it exists, just put
336 // it after the floating pointer. The fp size as of the 1.4 Intel MP
337 // specification is 0x10 bytes.
341 mpFloatingPointer
->setTableAddr(table
);
344 fpSize
= mpFloatingPointer
->writeOut(physProxy
, fp
);
346 tableSize
= mpConfigTable
->writeOut(physProxy
, table
);
350 // Do some bounds checking to make sure we at least didn't step on
351 // ourselves and the fp structure was the size we thought it was.
352 assert(fp
> table
|| fp
+ fpSize
<= table
);
353 assert(table
> fp
|| table
+ tableSize
<= fp
);
354 assert(fpSize
== 0x10);
358 X86System::~X86System()
364 X86SystemParams::create()
366 return new X86System(this);