src/arch/x86/system.cc

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * Copyright (c) 2018 TU Dresden
   4  * All rights reserved.
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions are
  17  * met: redistributions of source code must retain the above copyright
  18  * notice, this list of conditions and the following disclaimer;
  19  * redistributions in binary form must reproduce the above copyright
  20  * notice, this list of conditions and the following disclaimer in the
  21  * documentation and/or other materials provided with the distribution;
  22  * neither the name of the copyright holders nor the names of its
  23  * contributors may be used to endorse or promote products derived from
  24  * this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  * Authors: Gabe Black
  39  *          Maximilian Stein
  40  */
  41
  42 #include "arch/x86/system.hh"
  43
  44 #include "arch/x86/bios/intelmp.hh"
  45 #include "arch/x86/bios/smbios.hh"
  46 #include "arch/x86/isa_traits.hh"
  47 #include "base/loader/object_file.hh"
  48 #include "cpu/thread_context.hh"
  49 #include "params/X86System.hh"
  50
  51 using namespace X86ISA;
  52
  53 X86System::X86System(Params *p) :
  54     System(p), smbiosTable(p->smbios_table),
  55     mpFloatingPointer(p->intel_mp_pointer),
  56     mpConfigTable(p->intel_mp_table),
  57     rsdp(p->acpi_description_table_pointer)
  58 {
  59 }
  60
  61 void
  62 X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
  63         SegDescriptor desc, bool longmode)
  64 {
  65     bool honorBase = !longmode || seg == SEGMENT_REG_FS ||
  66                                   seg == SEGMENT_REG_GS ||
  67                                   seg == SEGMENT_REG_TSL ||
  68                                   seg == SYS_SEGMENT_REG_TR;
  69
  70     SegAttr attr = 0;
  71
  72     attr.dpl = desc.dpl;
  73     attr.unusable = 0;
  74     attr.defaultSize = desc.d;
  75     attr.longMode = desc.l;
  76     attr.avl = desc.avl;
  77     attr.granularity = desc.g;
  78     attr.present = desc.p;
  79     attr.system = desc.s;
  80     attr.type = desc.type;
  81     if (desc.s) {
  82         if (desc.type.codeOrData) {
  83             // Code segment
  84             attr.expandDown = 0;
  85             attr.readable = desc.type.r;
  86             attr.writable = 0;
  87         } else {
  88             // Data segment
  89             attr.expandDown = desc.type.e;
  90             attr.readable = 1;
  91             attr.writable = desc.type.w;
  92         }
  93     } else {
  94         attr.readable = 1;
  95         attr.writable = 1;
  96         attr.expandDown = 0;
  97     }
  98
  99     tc->setMiscReg(MISCREG_SEG_BASE(seg), desc.base);
 100     tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? desc.base : 0);
 101     tc->setMiscReg(MISCREG_SEG_LIMIT(seg), desc.limit);
 102     tc->setMiscReg(MISCREG_SEG_ATTR(seg), (RegVal)attr);
 103 }
 104
 105 void
 106 X86System::initState()
 107 {
 108     System::initState();
 109
 110     if (!kernel)
 111         fatal("No kernel to load.\n");
 112
 113     if (kernel->getArch() == ObjectFile::I386)
 114         fatal("Loading a 32 bit x86 kernel is not supported.\n");
 115
 116     ThreadContext *tc = threadContexts[0];
 117     // This is the boot strap processor (BSP). Initialize it to look like
 118     // the boot loader has just turned control over to the 64 bit OS. We
 119     // won't actually set up real mode or legacy protected mode descriptor
 120     // tables because we aren't executing any code that would require
 121     // them. We do, however toggle the control bits in the correct order
 122     // while allowing consistency checks and the underlying mechansims
 123     // just to be safe.
 124
 125     const int NumPDTs = 4;
 126
 127     const Addr PageMapLevel4 = 0x70000;
 128     const Addr PageDirPtrTable = 0x71000;
 129     const Addr PageDirTable[NumPDTs] =
 130         {0x72000, 0x73000, 0x74000, 0x75000};
 131     const Addr GDTBase = 0x76000;
 132
 133     const int PML4Bits = 9;
 134     const int PDPTBits = 9;
 135     const int PDTBits = 9;
 136
 137     /*
 138      * Set up the gdt.
 139      */
 140     uint8_t numGDTEntries = 0;
 141     // Place holder at selector 0
 142     uint64_t nullDescriptor = 0;
 143     physProxy.writeBlob(GDTBase + numGDTEntries * 8, &nullDescriptor, 8);
 144     numGDTEntries++;
 145
 146     SegDescriptor initDesc = 0;
 147     initDesc.type.codeOrData = 0; // code or data type
 148     initDesc.type.c = 0;          // conforming
 149     initDesc.type.r = 1;          // readable
 150     initDesc.dpl = 0;             // privilege
 151     initDesc.p = 1;               // present
 152     initDesc.l = 1;               // longmode - 64 bit
 153     initDesc.d = 0;               // operand size
 154     initDesc.g = 1;               // granularity
 155     initDesc.s = 1;               // system segment
 156     initDesc.limit = 0xFFFFFFFF;
 157     initDesc.base = 0;
 158
 159     // 64 bit code segment
 160     SegDescriptor csDesc = initDesc;
 161     csDesc.type.codeOrData = 1;
 162     csDesc.dpl = 0;
 163     // Because we're dealing with a pointer and I don't think it's
 164     // guaranteed that there isn't anything in a nonvirtual class between
 165     // it's beginning in memory and it's actual data, we'll use an
 166     // intermediary.
 167     uint64_t csDescVal = csDesc;
 168     physProxy.writeBlob(GDTBase + numGDTEntries * 8, (&csDescVal), 8);
 169
 170     numGDTEntries++;
 171
 172     SegSelector cs = 0;
 173     cs.si = numGDTEntries - 1;
 174
 175     tc->setMiscReg(MISCREG_CS, (RegVal)cs);
 176
 177     // 32 bit data segment
 178     SegDescriptor dsDesc = initDesc;
 179     uint64_t dsDescVal = dsDesc;
 180     physProxy.writeBlob(GDTBase + numGDTEntries * 8, (&dsDescVal), 8);
 181
 182     numGDTEntries++;
 183
 184     SegSelector ds = 0;
 185     ds.si = numGDTEntries - 1;
 186
 187     tc->setMiscReg(MISCREG_DS, (RegVal)ds);
 188     tc->setMiscReg(MISCREG_ES, (RegVal)ds);
 189     tc->setMiscReg(MISCREG_FS, (RegVal)ds);
 190     tc->setMiscReg(MISCREG_GS, (RegVal)ds);
 191     tc->setMiscReg(MISCREG_SS, (RegVal)ds);
 192
 193     tc->setMiscReg(MISCREG_TSL, 0);
 194     tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
 195     tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
 196
 197     SegDescriptor tssDesc = initDesc;
 198     uint64_t tssDescVal = tssDesc;
 199     physProxy.writeBlob(GDTBase + numGDTEntries * 8, (&tssDescVal), 8);
 200
 201     numGDTEntries++;
 202
 203     SegSelector tss = 0;
 204     tss.si = numGDTEntries - 1;
 205
 206     tc->setMiscReg(MISCREG_TR, (RegVal)tss);
 207     installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true);
 208
 209     /*
 210      * Identity map the first 4GB of memory. In order to map this region
 211      * of memory in long mode, there needs to be one actual page map level
 212      * 4 entry which points to one page directory pointer table which
 213      * points to 4 different page directory tables which are full of two
 214      * megabyte pages. All of the other entries in valid tables are set
 215      * to indicate that they don't pertain to anything valid and will
 216      * cause a fault if used.
 217      */
 218
 219     // Put valid values in all of the various table entries which indicate
 220     // that those entries don't point to further tables or pages. Then
 221     // set the values of those entries which are needed.
 222
 223     // Page Map Level 4
 224
 225     // read/write, user, not present
 226     uint64_t pml4e = htole<uint64_t>(0x6);
 227     for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
 228         physProxy.writeBlob(PageMapLevel4 + offset, (&pml4e), 8);
 229     }
 230     // Point to the only PDPT
 231     pml4e = htole<uint64_t>(0x7 | PageDirPtrTable);
 232     physProxy.writeBlob(PageMapLevel4, (&pml4e), 8);
 233
 234     // Page Directory Pointer Table
 235
 236     // read/write, user, not present
 237     uint64_t pdpe = htole<uint64_t>(0x6);
 238     for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8)
 239         physProxy.writeBlob(PageDirPtrTable + offset, &pdpe, 8);
 240     // Point to the PDTs
 241     for (int table = 0; table < NumPDTs; table++) {
 242         pdpe = htole<uint64_t>(0x7 | PageDirTable[table]);
 243         physProxy.writeBlob(PageDirPtrTable + table * 8, &pdpe, 8);
 244     }
 245
 246     // Page Directory Tables
 247
 248     Addr base = 0;
 249     const Addr pageSize = 2 << 20;
 250     for (int table = 0; table < NumPDTs; table++) {
 251         for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
 252             // read/write, user, present, 4MB
 253             uint64_t pdte = htole(0x87 | base);
 254             physProxy.writeBlob(PageDirTable[table] + offset, &pdte, 8);
 255             base += pageSize;
 256         }
 257     }
 258
 259     /*
 260      * Transition from real mode all the way up to Long mode
 261      */
 262     CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
 263     // Turn off paging.
 264     cr0.pg = 0;
 265     tc->setMiscReg(MISCREG_CR0, cr0);
 266     // Turn on protected mode.
 267     cr0.pe = 1;
 268     tc->setMiscReg(MISCREG_CR0, cr0);
 269
 270     CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
 271     // Turn on pae.
 272     cr4.pae = 1;
 273     tc->setMiscReg(MISCREG_CR4, cr4);
 274
 275     // Point to the page tables.
 276     tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
 277
 278     Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
 279     // Enable long mode.
 280     efer.lme = 1;
 281     tc->setMiscReg(MISCREG_EFER, efer);
 282
 283     // Start using longmode segments.
 284     installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
 285     installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
 286     installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
 287     installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
 288     installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
 289     installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
 290
 291     // Activate long mode.
 292     cr0.pg = 1;
 293     tc->setMiscReg(MISCREG_CR0, cr0);
 294
 295     tc->pcState(tc->getSystemPtr()->kernelEntry);
 296
 297     // We should now be in long mode. Yay!
 298
 299     Addr ebdaPos = 0xF0000;
 300     Addr fixed, table;
 301
 302     // Write out the SMBios/DMI table.
 303     writeOutSMBiosTable(ebdaPos, fixed, table);
 304     ebdaPos += (fixed + table);
 305     ebdaPos = roundUp(ebdaPos, 16);
 306
 307     // Write out the Intel MP Specification configuration table.
 308     writeOutMPTable(ebdaPos, fixed, table);
 309     ebdaPos += (fixed + table);
 310 }
 311
 312 void
 313 X86System::writeOutSMBiosTable(Addr header,
 314         Addr &headerSize, Addr &structSize, Addr table)
 315 {
 316     // If the table location isn't specified, just put it after the header.
 317     // The header size as of the 2.5 SMBios specification is 0x1F bytes.
 318     if (!table)
 319         table = header + 0x1F;
 320     smbiosTable->setTableAddr(table);
 321
 322     smbiosTable->writeOut(physProxy, header, headerSize, structSize);
 323
 324     // Do some bounds checking to make sure we at least didn't step on
 325     // ourselves.
 326     assert(header > table || header + headerSize <= table);
 327     assert(table > header || table + structSize <= header);
 328 }
 329
 330 void
 331 X86System::writeOutMPTable(Addr fp,
 332         Addr &fpSize, Addr &tableSize, Addr table)
 333 {
 334     // If the table location isn't specified and it exists, just put
 335     // it after the floating pointer. The fp size as of the 1.4 Intel MP
 336     // specification is 0x10 bytes.
 337     if (mpConfigTable) {
 338         if (!table)
 339             table = fp + 0x10;
 340         mpFloatingPointer->setTableAddr(table);
 341     }
 342
 343     fpSize = mpFloatingPointer->writeOut(physProxy, fp);
 344     if (mpConfigTable)
 345         tableSize = mpConfigTable->writeOut(physProxy, table);
 346     else
 347         tableSize = 0;
 348
 349     // Do some bounds checking to make sure we at least didn't step on
 350     // ourselves and the fp structure was the size we thought it was.
 351     assert(fp > table || fp + fpSize <= table);
 352     assert(table > fp || table + tableSize <= fp);
 353     assert(fpSize == 0x10);
 354 }
 355
 356
 357 X86System::~X86System()
 358 {
 359     delete smbiosTable;
 360 }
 361
 362 X86System *
 363 X86SystemParams::create()
 364 {
 365     return new X86System(this);
 366 }