2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
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18 * redistributions in binary form must reproduce the above copyright
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23 * this software without specific prior written permission.
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42 #include "arch/x86/insts/microldstop.hh"
43 #include "arch/x86/regs/misc.hh"
44 #include "arch/x86/regs/msr.hh"
45 #include "arch/x86/faults.hh"
46 #include "arch/x86/pagetable.hh"
47 #include "arch/x86/pagetable_walker.hh"
48 #include "arch/x86/tlb.hh"
49 #include "arch/x86/x86_traits.hh"
50 #include "base/bitfield.hh"
51 #include "base/trace.hh"
52 #include "cpu/base.hh"
53 #include "cpu/thread_context.hh"
54 #include "debug/TLB.hh"
55 #include "mem/packet_access.hh"
56 #include "mem/page_table.hh"
57 #include "mem/request.hh"
58 #include "sim/full_system.hh"
59 #include "sim/process.hh"
63 TLB::TLB(const Params
*p
) : BaseTLB(p
), configAddress(0), size(p
->size
)
65 tlb
= new TlbEntry
[size
];
66 std::memset(tlb
, 0, sizeof(TlbEntry
) * size
);
68 for (int x
= 0; x
< size
; x
++)
69 freeList
.push_back(&tlb
[x
]);
76 TLB::insert(Addr vpn
, TlbEntry
&entry
)
78 //TODO Deal with conflicting entries
80 TlbEntry
*newEntry
= NULL
;
81 if (!freeList
.empty()) {
82 newEntry
= freeList
.front();
85 newEntry
= entryList
.back();
89 newEntry
->vaddr
= vpn
;
90 entryList
.push_front(newEntry
);
94 TLB::EntryList::iterator
95 TLB::lookupIt(Addr va
, bool update_lru
)
97 //TODO make this smarter at some point
98 EntryList::iterator entry
;
99 for (entry
= entryList
.begin(); entry
!= entryList
.end(); entry
++) {
100 if ((*entry
)->vaddr
<= va
&& (*entry
)->vaddr
+ (*entry
)->size
> va
) {
101 DPRINTF(TLB
, "Matched vaddr %#x to entry starting at %#x "
102 "with size %#x.\n", va
, (*entry
)->vaddr
, (*entry
)->size
);
104 entryList
.push_front(*entry
);
105 entryList
.erase(entry
);
106 entry
= entryList
.begin();
115 TLB::lookup(Addr va
, bool update_lru
)
117 EntryList::iterator entry
= lookupIt(va
, update_lru
);
118 if (entry
== entryList
.end())
127 DPRINTF(TLB
, "Invalidating all entries.\n");
128 while (!entryList
.empty()) {
129 TlbEntry
*entry
= entryList
.front();
130 entryList
.pop_front();
131 freeList
.push_back(entry
);
136 TLB::setConfigAddress(uint32_t addr
)
138 configAddress
= addr
;
142 TLB::invalidateNonGlobal()
144 DPRINTF(TLB
, "Invalidating all non global entries.\n");
145 EntryList::iterator entryIt
;
146 for (entryIt
= entryList
.begin(); entryIt
!= entryList
.end();) {
147 if (!(*entryIt
)->global
) {
148 freeList
.push_back(*entryIt
);
149 entryList
.erase(entryIt
++);
157 TLB::demapPage(Addr va
, uint64_t asn
)
159 EntryList::iterator entry
= lookupIt(va
, false);
160 if (entry
!= entryList
.end()) {
161 freeList
.push_back(*entry
);
162 entryList
.erase(entry
);
167 TLB::translateInt(RequestPtr req
, ThreadContext
*tc
)
169 DPRINTF(TLB
, "Addresses references internal memory.\n");
170 Addr vaddr
= req
->getVaddr();
171 Addr prefix
= (vaddr
>> 3) & IntAddrPrefixMask
;
172 if (prefix
== IntAddrPrefixCPUID
) {
173 panic("CPUID memory space not yet implemented!\n");
174 } else if (prefix
== IntAddrPrefixMSR
) {
175 vaddr
= (vaddr
>> 3) & ~IntAddrPrefixMask
;
176 req
->setFlags(Request::MMAPPED_IPR
);
179 if (!msrAddrToIndex(regNum
, vaddr
))
180 return new GeneralProtection(0);
182 //The index is multiplied by the size of a MiscReg so that
183 //any memory dependence calculations will not see these as
185 req
->setPaddr((Addr
)regNum
* sizeof(MiscReg
));
187 } else if (prefix
== IntAddrPrefixIO
) {
188 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
189 // bitmap in the TSS.
191 Addr IOPort
= vaddr
& ~IntAddrPrefixMask
;
192 // Make sure the address fits in the expected 16 bit IO address
194 assert(!(IOPort
& ~0xFFFF));
195 if (IOPort
== 0xCF8 && req
->getSize() == 4) {
196 req
->setFlags(Request::MMAPPED_IPR
);
197 req
->setPaddr(MISCREG_PCI_CONFIG_ADDRESS
* sizeof(MiscReg
));
198 } else if ((IOPort
& ~mask(2)) == 0xCFC) {
199 req
->setFlags(Request::UNCACHEABLE
);
201 tc
->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS
);
202 if (bits(configAddress
, 31, 31)) {
203 req
->setPaddr(PhysAddrPrefixPciConfig
|
204 mbits(configAddress
, 30, 2) |
207 req
->setPaddr(PhysAddrPrefixIO
| IOPort
);
210 req
->setFlags(Request::UNCACHEABLE
);
211 req
->setPaddr(PhysAddrPrefixIO
| IOPort
);
215 panic("Access to unrecognized internal address space %#x.\n",
221 TLB::translate(RequestPtr req
, ThreadContext
*tc
, Translation
*translation
,
222 Mode mode
, bool &delayedResponse
, bool timing
)
224 uint32_t flags
= req
->getFlags();
225 int seg
= flags
& SegmentFlagMask
;
226 bool storeCheck
= flags
& (StoreCheck
<< FlagShift
);
228 delayedResponse
= false;
230 // If this is true, we're dealing with a request to a non-memory address
232 if (seg
== SEGMENT_REG_MS
) {
233 return translateInt(req
, tc
);
236 Addr vaddr
= req
->getVaddr();
237 DPRINTF(TLB
, "Translating vaddr %#x.\n", vaddr
);
239 HandyM5Reg m5Reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
241 // If protected mode has been enabled...
243 DPRINTF(TLB
, "In protected mode.\n");
244 // If we're not in 64-bit mode, do protection/limit checks
245 if (m5Reg
.mode
!= LongMode
) {
246 DPRINTF(TLB
, "Not in long mode. Checking segment protection.\n");
247 // Check for a NULL segment selector.
248 if (!(seg
== SEGMENT_REG_TSG
|| seg
== SYS_SEGMENT_REG_IDTR
||
249 seg
== SEGMENT_REG_HS
|| seg
== SEGMENT_REG_LS
)
250 && !tc
->readMiscRegNoEffect(MISCREG_SEG_SEL(seg
)))
251 return new GeneralProtection(0);
252 bool expandDown
= false;
253 SegAttr attr
= tc
->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg
));
254 if (seg
>= SEGMENT_REG_ES
&& seg
<= SEGMENT_REG_HS
) {
255 if (!attr
.writable
&& (mode
== Write
|| storeCheck
))
256 return new GeneralProtection(0);
257 if (!attr
.readable
&& mode
== Read
)
258 return new GeneralProtection(0);
259 expandDown
= attr
.expandDown
;
262 Addr base
= tc
->readMiscRegNoEffect(MISCREG_SEG_BASE(seg
));
263 Addr limit
= tc
->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg
));
264 // This assumes we're not in 64 bit mode. If we were, the default
265 // address size is 64 bits, overridable to 32.
267 bool sizeOverride
= (flags
& (AddrSizeFlagBit
<< FlagShift
));
268 SegAttr csAttr
= tc
->readMiscRegNoEffect(MISCREG_CS_ATTR
);
269 if ((csAttr
.defaultSize
&& sizeOverride
) ||
270 (!csAttr
.defaultSize
&& !sizeOverride
))
272 Addr offset
= bits(vaddr
- base
, size
-1, 0);
273 Addr endOffset
= offset
+ req
->getSize() - 1;
275 DPRINTF(TLB
, "Checking an expand down segment.\n");
276 warn_once("Expand down segments are untested.\n");
277 if (offset
<= limit
|| endOffset
<= limit
)
278 return new GeneralProtection(0);
280 if (offset
> limit
|| endOffset
> limit
)
281 return new GeneralProtection(0);
284 // If paging is enabled, do the translation.
286 DPRINTF(TLB
, "Paging enabled.\n");
287 // The vaddr already has the segment base applied.
288 TlbEntry
*entry
= lookup(vaddr
);
291 Fault fault
= walker
->start(tc
, translation
, req
, mode
);
292 if (timing
|| fault
!= NoFault
) {
293 // This gets ignored in atomic mode.
294 delayedResponse
= true;
297 entry
= lookup(vaddr
);
300 DPRINTF(TLB
, "Handling a TLB miss for "
301 "address %#x at pc %#x.\n",
302 vaddr
, tc
->instAddr());
304 Process
*p
= tc
->getProcessPtr();
306 bool success
= p
->pTable
->lookup(vaddr
, newEntry
);
307 if (!success
&& mode
!= Execute
) {
308 // Check if we just need to grow the stack.
309 if (p
->fixupStackFault(vaddr
)) {
310 // If we did, lookup the entry for the new page.
311 success
= p
->pTable
->lookup(vaddr
, newEntry
);
315 return new PageFault(vaddr
, true, mode
, true, false);
317 Addr alignedVaddr
= p
->pTable
->pageAlign(vaddr
);
318 DPRINTF(TLB
, "Mapping %#x to %#x\n", alignedVaddr
,
319 newEntry
.pageStart());
320 entry
= insert(alignedVaddr
, newEntry
);
322 DPRINTF(TLB
, "Miss was serviced.\n");
326 DPRINTF(TLB
, "Entry found with paddr %#x, "
327 "doing protection checks.\n", entry
->paddr
);
328 // Do paging protection checks.
329 bool inUser
= (m5Reg
.cpl
== 3 &&
330 !(flags
& (CPL0FlagBit
<< FlagShift
)));
331 CR0 cr0
= tc
->readMiscRegNoEffect(MISCREG_CR0
);
332 bool badWrite
= (!entry
->writable
&& (inUser
|| cr0
.wp
));
333 if ((inUser
&& !entry
->user
) || (mode
== Write
&& badWrite
)) {
334 // The page must have been present to get into the TLB in
335 // the first place. We'll assume the reserved bits are
336 // fine even though we're not checking them.
337 return new PageFault(vaddr
, true, mode
, inUser
, false);
339 if (storeCheck
&& badWrite
) {
340 // This would fault if this were a write, so return a page
341 // fault that reflects that happening.
342 return new PageFault(vaddr
, true, Write
, inUser
, false);
345 Addr paddr
= entry
->paddr
| (vaddr
& (entry
->size
-1));
346 DPRINTF(TLB
, "Translated %#x -> %#x.\n", vaddr
, paddr
);
347 req
->setPaddr(paddr
);
348 if (entry
->uncacheable
)
349 req
->setFlags(Request::UNCACHEABLE
);
351 //Use the address which already has segmentation applied.
352 DPRINTF(TLB
, "Paging disabled.\n");
353 DPRINTF(TLB
, "Translated %#x -> %#x.\n", vaddr
, vaddr
);
354 req
->setPaddr(vaddr
);
358 DPRINTF(TLB
, "In real mode.\n");
359 DPRINTF(TLB
, "Translated %#x -> %#x.\n", vaddr
, vaddr
);
360 req
->setPaddr(vaddr
);
362 // Check for an access to the local APIC
364 LocalApicBase localApicBase
=
365 tc
->readMiscRegNoEffect(MISCREG_APIC_BASE
);
366 Addr baseAddr
= localApicBase
.base
* PageBytes
;
367 Addr paddr
= req
->getPaddr();
368 if (baseAddr
<= paddr
&& baseAddr
+ PageBytes
> paddr
) {
369 // The Intel developer's manuals say the below restrictions apply,
370 // but the linux kernel, because of a compiler optimization, breaks
374 if (paddr & ((32/8) - 1))
375 return new GeneralProtection(0);
377 if (req->getSize() != (32/8))
378 return new GeneralProtection(0);
380 // Force the access to be uncacheable.
381 req
->setFlags(Request::UNCACHEABLE
);
382 req
->setPaddr(x86LocalAPICAddress(tc
->contextId(),
390 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
392 bool delayedResponse
;
393 return TLB::translate(req
, tc
, NULL
, mode
, delayedResponse
, false);
397 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
398 Translation
*translation
, Mode mode
)
400 bool delayedResponse
;
403 TLB::translate(req
, tc
, translation
, mode
, delayedResponse
, true);
404 if (!delayedResponse
)
405 translation
->finish(fault
, req
, tc
, mode
);
415 TLB::serialize(std::ostream
&os
)
420 TLB::unserialize(Checkpoint
*cp
, const std::string
§ion
)
427 return walker
->getPort("port");
430 } // namespace X86ISA
433 X86TLBParams::create()
435 return new X86ISA::TLB(this);