src/arch/x86/tlb.cc

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
   7  * following conditions are met:
   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
  11  * compensation for, or commercial advantage from such use.  Illustrative
  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
  14  * Illustrative examples of commercial use are distributing products for
  15  * commercial advantage and providing services using the software for
  16  * commercial advantage.
  17  *
  18  * If you wish to use this software or functionality therein that may be
  19  * covered by patents for commercial use, please contact:
  20  *     Director of Intellectual Property Licensing
  21  *     Office of Strategy and Technology
  22  *     Hewlett-Packard Company
  23  *     1501 Page Mill Road
  24  *     Palo Alto, California  94304
  25  *
  26  * Redistributions of source code must retain the above copyright notice,
  27  * this list of conditions and the following disclaimer.  Redistributions
  28  * in binary form must reproduce the above copyright notice, this list of
  29  * conditions and the following disclaimer in the documentation and/or
  30  * other materials provided with the distribution.  Neither the name of
  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  32  * contributors may be used to endorse or promote products derived from
  33  * this software without specific prior written permission.  No right of
  34  * sublicense is granted herewith.  Derivatives of the software and
  35  * output created using the software may be prepared, but only for
  36  * Non-Commercial Uses.  Derivatives of the software may be shared with
  37  * others provided: (i) the others agree to abide by the list of
  38  * conditions herein which includes the Non-Commercial Use restrictions;
  39  * and (ii) such Derivatives of the software include the above copyright
  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #include <cstring>
  59
  60 #include "config/full_system.hh"
  61
  62 #include "arch/x86/pagetable.hh"
  63 #include "arch/x86/tlb.hh"
  64 #include "arch/x86/x86_traits.hh"
  65 #include "base/bitfield.hh"
  66 #include "base/trace.hh"
  67 #include "config/full_system.hh"
  68 #include "cpu/thread_context.hh"
  69 #include "cpu/base.hh"
  70 #include "mem/packet_access.hh"
  71 #include "mem/request.hh"
  72
  73 #if FULL_SYSTEM
  74 #include "arch/x86/pagetable_walker.hh"
  75 #endif
  76
  77 namespace X86ISA {
  78
  79 TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
  80 {
  81     tlb = new TlbEntry[size];
  82     std::memset(tlb, 0, sizeof(TlbEntry) * size);
  83
  84     for (int x = 0; x < size; x++)
  85         freeList.push_back(&tlb[x]);
  86
  87 #if FULL_SYSTEM
  88     walker = p->walker;
  89     walker->setTLB(this);
  90 #endif
  91 }
  92
  93 void
  94 TLB::insert(Addr vpn, TlbEntry &entry)
  95 {
  96     //TODO Deal with conflicting entries
  97
  98     TlbEntry *newEntry = NULL;
  99     if (!freeList.empty()) {
 100         newEntry = freeList.front();
 101         freeList.pop_front();
 102     } else {
 103         newEntry = entryList.back();
 104         entryList.pop_back();
 105     }
 106     *newEntry = entry;
 107     newEntry->vaddr = vpn;
 108     entryList.push_front(newEntry);
 109 }
 110
 111 TlbEntry *
 112 TLB::lookup(Addr va, bool update_lru)
 113 {
 114     //TODO make this smarter at some point
 115     EntryList::iterator entry;
 116     for (entry = entryList.begin(); entry != entryList.end(); entry++) {
 117         if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) {
 118             DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x "
 119                     "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size);
 120             TlbEntry *e = *entry;
 121             if (update_lru) {
 122                 entryList.erase(entry);
 123                 entryList.push_front(e);
 124             }
 125             return e;
 126         }
 127     }
 128     return NULL;
 129 }
 130
 131 #if FULL_SYSTEM
 132 void
 133 TLB::walk(ThreadContext * _tc, Addr vaddr)
 134 {
 135     walker->start(_tc, vaddr);
 136 }
 137 #endif
 138
 139 void
 140 TLB::invalidateAll()
 141 {
 142     DPRINTF(TLB, "Invalidating all entries.\n");
 143     while (!entryList.empty()) {
 144         TlbEntry *entry = entryList.front();
 145         entryList.pop_front();
 146         freeList.push_back(entry);
 147     }
 148 }
 149
 150 void
 151 TLB::setConfigAddress(uint32_t addr)
 152 {
 153     configAddress = addr;
 154 }
 155
 156 void
 157 TLB::invalidateNonGlobal()
 158 {
 159     DPRINTF(TLB, "Invalidating all non global entries.\n");
 160     EntryList::iterator entryIt;
 161     for (entryIt = entryList.begin(); entryIt != entryList.end();) {
 162         if (!(*entryIt)->global) {
 163             freeList.push_back(*entryIt);
 164             entryList.erase(entryIt++);
 165         } else {
 166             entryIt++;
 167         }
 168     }
 169 }
 170
 171 void
 172 TLB::demapPage(Addr va, uint64_t asn)
 173 {
 174     EntryList::iterator entry = lookupIt(va, false);
 175     if (entry != entryList.end()) {
 176         freeList.push_back(*entry);
 177         entryList.erase(entry);
 178     }
 179 }
 180
 181 template<class TlbFault>
 182 Fault
 183 TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
 184 {
 185     Addr vaddr = req->getVaddr();
 186     DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
 187     uint32_t flags = req->getFlags();
 188     bool storeCheck = flags & StoreCheck;
 189
 190     int seg = flags & mask(4);
 191
 192     //XXX Junk code to surpress the warning
 193     if (storeCheck);
 194
 195     // If this is true, we're dealing with a request to read an internal
 196     // value.
 197     if (seg == SEGMENT_REG_MS) {
 198         DPRINTF(TLB, "Addresses references internal memory.\n");
 199         Addr prefix = vaddr & IntAddrPrefixMask;
 200         if (prefix == IntAddrPrefixCPUID) {
 201             panic("CPUID memory space not yet implemented!\n");
 202         } else if (prefix == IntAddrPrefixMSR) {
 203             req->setMmapedIpr(true);
 204             Addr regNum = 0;
 205             switch (vaddr & ~IntAddrPrefixMask) {
 206               case 0x10:
 207                 regNum = MISCREG_TSC;
 208                 break;
 209               case 0xFE:
 210                 regNum = MISCREG_MTRRCAP;
 211                 break;
 212               case 0x174:
 213                 regNum = MISCREG_SYSENTER_CS;
 214                 break;
 215               case 0x175:
 216                 regNum = MISCREG_SYSENTER_ESP;
 217                 break;
 218               case 0x176:
 219                 regNum = MISCREG_SYSENTER_EIP;
 220                 break;
 221               case 0x179:
 222                 regNum = MISCREG_MCG_CAP;
 223                 break;
 224               case 0x17A:
 225                 regNum = MISCREG_MCG_STATUS;
 226                 break;
 227               case 0x17B:
 228                 regNum = MISCREG_MCG_CTL;
 229                 break;
 230               case 0x1D9:
 231                 regNum = MISCREG_DEBUG_CTL_MSR;
 232                 break;
 233               case 0x1DB:
 234                 regNum = MISCREG_LAST_BRANCH_FROM_IP;
 235                 break;
 236               case 0x1DC:
 237                 regNum = MISCREG_LAST_BRANCH_TO_IP;
 238                 break;
 239               case 0x1DD:
 240                 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
 241                 break;
 242               case 0x1DE:
 243                 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
 244                 break;
 245               case 0x200:
 246                 regNum = MISCREG_MTRR_PHYS_BASE_0;
 247                 break;
 248               case 0x201:
 249                 regNum = MISCREG_MTRR_PHYS_MASK_0;
 250                 break;
 251               case 0x202:
 252                 regNum = MISCREG_MTRR_PHYS_BASE_1;
 253                 break;
 254               case 0x203:
 255                 regNum = MISCREG_MTRR_PHYS_MASK_1;
 256                 break;
 257               case 0x204:
 258                 regNum = MISCREG_MTRR_PHYS_BASE_2;
 259                 break;
 260               case 0x205:
 261                 regNum = MISCREG_MTRR_PHYS_MASK_2;
 262                 break;
 263               case 0x206:
 264                 regNum = MISCREG_MTRR_PHYS_BASE_3;
 265                 break;
 266               case 0x207:
 267                 regNum = MISCREG_MTRR_PHYS_MASK_3;
 268                 break;
 269               case 0x208:
 270                 regNum = MISCREG_MTRR_PHYS_BASE_4;
 271                 break;
 272               case 0x209:
 273                 regNum = MISCREG_MTRR_PHYS_MASK_4;
 274                 break;
 275               case 0x20A:
 276                 regNum = MISCREG_MTRR_PHYS_BASE_5;
 277                 break;
 278               case 0x20B:
 279                 regNum = MISCREG_MTRR_PHYS_MASK_5;
 280                 break;
 281               case 0x20C:
 282                 regNum = MISCREG_MTRR_PHYS_BASE_6;
 283                 break;
 284               case 0x20D:
 285                 regNum = MISCREG_MTRR_PHYS_MASK_6;
 286                 break;
 287               case 0x20E:
 288                 regNum = MISCREG_MTRR_PHYS_BASE_7;
 289                 break;
 290               case 0x20F:
 291                 regNum = MISCREG_MTRR_PHYS_MASK_7;
 292                 break;
 293               case 0x250:
 294                 regNum = MISCREG_MTRR_FIX_64K_00000;
 295                 break;
 296               case 0x258:
 297                 regNum = MISCREG_MTRR_FIX_16K_80000;
 298                 break;
 299               case 0x259:
 300                 regNum = MISCREG_MTRR_FIX_16K_A0000;
 301                 break;
 302               case 0x268:
 303                 regNum = MISCREG_MTRR_FIX_4K_C0000;
 304                 break;
 305               case 0x269:
 306                 regNum = MISCREG_MTRR_FIX_4K_C8000;
 307                 break;
 308               case 0x26A:
 309                 regNum = MISCREG_MTRR_FIX_4K_D0000;
 310                 break;
 311               case 0x26B:
 312                 regNum = MISCREG_MTRR_FIX_4K_D8000;
 313                 break;
 314               case 0x26C:
 315                 regNum = MISCREG_MTRR_FIX_4K_E0000;
 316                 break;
 317               case 0x26D:
 318                 regNum = MISCREG_MTRR_FIX_4K_E8000;
 319                 break;
 320               case 0x26E:
 321                 regNum = MISCREG_MTRR_FIX_4K_F0000;
 322                 break;
 323               case 0x26F:
 324                 regNum = MISCREG_MTRR_FIX_4K_F8000;
 325                 break;
 326               case 0x277:
 327                 regNum = MISCREG_PAT;
 328                 break;
 329               case 0x2FF:
 330                 regNum = MISCREG_DEF_TYPE;
 331                 break;
 332               case 0x400:
 333                 regNum = MISCREG_MC0_CTL;
 334                 break;
 335               case 0x404:
 336                 regNum = MISCREG_MC1_CTL;
 337                 break;
 338               case 0x408:
 339                 regNum = MISCREG_MC2_CTL;
 340                 break;
 341               case 0x40C:
 342                 regNum = MISCREG_MC3_CTL;
 343                 break;
 344               case 0x410:
 345                 regNum = MISCREG_MC4_CTL;
 346                 break;
 347               case 0x401:
 348                 regNum = MISCREG_MC0_STATUS;
 349                 break;
 350               case 0x405:
 351                 regNum = MISCREG_MC1_STATUS;
 352                 break;
 353               case 0x409:
 354                 regNum = MISCREG_MC2_STATUS;
 355                 break;
 356               case 0x40D:
 357                 regNum = MISCREG_MC3_STATUS;
 358                 break;
 359               case 0x411:
 360                 regNum = MISCREG_MC4_STATUS;
 361                 break;
 362               case 0x402:
 363                 regNum = MISCREG_MC0_ADDR;
 364                 break;
 365               case 0x406:
 366                 regNum = MISCREG_MC1_ADDR;
 367                 break;
 368               case 0x40A:
 369                 regNum = MISCREG_MC2_ADDR;
 370                 break;
 371               case 0x40E:
 372                 regNum = MISCREG_MC3_ADDR;
 373                 break;
 374               case 0x412:
 375                 regNum = MISCREG_MC4_ADDR;
 376                 break;
 377               case 0x403:
 378                 regNum = MISCREG_MC0_MISC;
 379                 break;
 380               case 0x407:
 381                 regNum = MISCREG_MC1_MISC;
 382                 break;
 383               case 0x40B:
 384                 regNum = MISCREG_MC2_MISC;
 385                 break;
 386               case 0x40F:
 387                 regNum = MISCREG_MC3_MISC;
 388                 break;
 389               case 0x413:
 390                 regNum = MISCREG_MC4_MISC;
 391                 break;
 392               case 0xC0000080:
 393                 regNum = MISCREG_EFER;
 394                 break;
 395               case 0xC0000081:
 396                 regNum = MISCREG_STAR;
 397                 break;
 398               case 0xC0000082:
 399                 regNum = MISCREG_LSTAR;
 400                 break;
 401               case 0xC0000083:
 402                 regNum = MISCREG_CSTAR;
 403                 break;
 404               case 0xC0000084:
 405                 regNum = MISCREG_SF_MASK;
 406                 break;
 407               case 0xC0000100:
 408                 regNum = MISCREG_FS_BASE;
 409                 break;
 410               case 0xC0000101:
 411                 regNum = MISCREG_GS_BASE;
 412                 break;
 413               case 0xC0000102:
 414                 regNum = MISCREG_KERNEL_GS_BASE;
 415                 break;
 416               case 0xC0000103:
 417                 regNum = MISCREG_TSC_AUX;
 418                 break;
 419               case 0xC0010000:
 420                 regNum = MISCREG_PERF_EVT_SEL0;
 421                 break;
 422               case 0xC0010001:
 423                 regNum = MISCREG_PERF_EVT_SEL1;
 424                 break;
 425               case 0xC0010002:
 426                 regNum = MISCREG_PERF_EVT_SEL2;
 427                 break;
 428               case 0xC0010003:
 429                 regNum = MISCREG_PERF_EVT_SEL3;
 430                 break;
 431               case 0xC0010004:
 432                 regNum = MISCREG_PERF_EVT_CTR0;
 433                 break;
 434               case 0xC0010005:
 435                 regNum = MISCREG_PERF_EVT_CTR1;
 436                 break;
 437               case 0xC0010006:
 438                 regNum = MISCREG_PERF_EVT_CTR2;
 439                 break;
 440               case 0xC0010007:
 441                 regNum = MISCREG_PERF_EVT_CTR3;
 442                 break;
 443               case 0xC0010010:
 444                 regNum = MISCREG_SYSCFG;
 445                 break;
 446               case 0xC0010016:
 447                 regNum = MISCREG_IORR_BASE0;
 448                 break;
 449               case 0xC0010017:
 450                 regNum = MISCREG_IORR_BASE1;
 451                 break;
 452               case 0xC0010018:
 453                 regNum = MISCREG_IORR_MASK0;
 454                 break;
 455               case 0xC0010019:
 456                 regNum = MISCREG_IORR_MASK1;
 457                 break;
 458               case 0xC001001A:
 459                 regNum = MISCREG_TOP_MEM;
 460                 break;
 461               case 0xC001001D:
 462                 regNum = MISCREG_TOP_MEM2;
 463                 break;
 464               case 0xC0010114:
 465                 regNum = MISCREG_VM_CR;
 466                 break;
 467               case 0xC0010115:
 468                 regNum = MISCREG_IGNNE;
 469                 break;
 470               case 0xC0010116:
 471                 regNum = MISCREG_SMM_CTL;
 472                 break;
 473               case 0xC0010117:
 474                 regNum = MISCREG_VM_HSAVE_PA;
 475                 break;
 476               default:
 477                 return new GeneralProtection(0);
 478             }
 479             //The index is multiplied by the size of a MiscReg so that
 480             //any memory dependence calculations will not see these as
 481             //overlapping.
 482             req->setPaddr(regNum * sizeof(MiscReg));
 483             return NoFault;
 484         } else if (prefix == IntAddrPrefixIO) {
 485             // TODO If CPL > IOPL or in virtual mode, check the I/O permission
 486             // bitmap in the TSS.
 487
 488             Addr IOPort = vaddr & ~IntAddrPrefixMask;
 489             // Make sure the address fits in the expected 16 bit IO address
 490             // space.
 491             assert(!(IOPort & ~0xFFFF));
 492             if (IOPort == 0xCF8 && req->getSize() == 4) {
 493                 req->setMmapedIpr(true);
 494                 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
 495             } else if ((IOPort & ~mask(2)) == 0xCFC) {
 496                 Addr configAddress =
 497                     tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
 498                 if (bits(configAddress, 31, 31)) {
 499                     req->setPaddr(PhysAddrPrefixPciConfig |
 500                             bits(configAddress, 30, 0));
 501                 }
 502             } else {
 503                 req->setPaddr(PhysAddrPrefixIO | IOPort);
 504             }
 505             return NoFault;
 506         } else {
 507             panic("Access to unrecognized internal address space %#x.\n",
 508                     prefix);
 509         }
 510     }
 511
 512     // Get cr0. This will tell us how to do translation. We'll assume it was
 513     // verified to be correct and consistent when set.
 514     CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
 515
 516     // If protected mode has been enabled...
 517     if (cr0.pe) {
 518         DPRINTF(TLB, "In protected mode.\n");
 519         Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
 520         SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
 521         // If we're not in 64-bit mode, do protection/limit checks
 522         if (!efer.lma || !csAttr.longMode) {
 523             DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
 524             SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
 525             if (!attr.writable && write)
 526                 return new GeneralProtection(0);
 527             if (!attr.readable && !write && !execute)
 528                 return new GeneralProtection(0);
 529             Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
 530             Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
 531             if (!attr.expandDown) {
 532                 DPRINTF(TLB, "Checking an expand down segment.\n");
 533                 // We don't have to worry about the access going around the
 534                 // end of memory because accesses will be broken up into
 535                 // pieces at boundaries aligned on sizes smaller than an
 536                 // entire address space. We do have to worry about the limit
 537                 // being less than the base.
 538                 if (limit < base) {
 539                     if (limit < vaddr + req->getSize() && vaddr < base)
 540                         return new GeneralProtection(0);
 541                 } else {
 542                     if (limit < vaddr + req->getSize())
 543                         return new GeneralProtection(0);
 544                 }
 545             } else {
 546                 if (limit < base) {
 547                     if (vaddr <= limit || vaddr + req->getSize() >= base)
 548                         return new GeneralProtection(0);
 549                 } else {
 550                     if (vaddr <= limit && vaddr + req->getSize() >= base)
 551                         return new GeneralProtection(0);
 552                 }
 553             }
 554         }
 555         // If paging is enabled, do the translation.
 556         if (cr0.pg) {
 557             DPRINTF(TLB, "Paging enabled.\n");
 558             // The vaddr already has the segment base applied.
 559             TlbEntry *entry = lookup(vaddr);
 560             if (!entry) {
 561                 return new TlbFault(vaddr);
 562             } else {
 563                 // Do paging protection checks.
 564                 DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr);
 565                 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
 566                 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
 567                 req->setPaddr(paddr);
 568             }
 569         } else {
 570             //Use the address which already has segmentation applied.
 571             DPRINTF(TLB, "Paging disabled.\n");
 572             DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
 573             req->setPaddr(vaddr);
 574         }
 575     } else {
 576         // Real mode
 577         DPRINTF(TLB, "In real mode.\n");
 578         DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
 579         req->setPaddr(vaddr);
 580     }
 581     return NoFault;
 582 };
 583
 584 Fault
 585 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 586 {
 587     return TLB::translate<FakeDTLBFault>(req, tc, write, false);
 588 }
 589
 590 Fault
 591 ITB::translate(RequestPtr &req, ThreadContext *tc)
 592 {
 593     return TLB::translate<FakeITLBFault>(req, tc, false, true);
 594 }
 595
 596 #if FULL_SYSTEM
 597
 598 Tick
 599 DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 600 {
 601     return tc->getCpuPtr()->ticks(1);
 602 }
 603
 604 Tick
 605 DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
 606 {
 607     return tc->getCpuPtr()->ticks(1);
 608 }
 609
 610 #endif
 611
 612 void
 613 TLB::serialize(std::ostream &os)
 614 {
 615 }
 616
 617 void
 618 TLB::unserialize(Checkpoint *cp, const std::string &section)
 619 {
 620 }
 621
 622 void
 623 DTB::serialize(std::ostream &os)
 624 {
 625     TLB::serialize(os);
 626 }
 627
 628 void
 629 DTB::unserialize(Checkpoint *cp, const std::string &section)
 630 {
 631     TLB::unserialize(cp, section);
 632 }
 633
 634 /* end namespace X86ISA */ }
 635
 636 X86ISA::ITB *
 637 X86ITBParams::create()
 638 {
 639     return new X86ISA::ITB(this);
 640 }
 641
 642 X86ISA::DTB *
 643 X86DTBParams::create()
 644 {
 645     return new X86ISA::DTB(this);
 646 }