2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include "arch/generic/mmapped_ipr.hh"
43 #include "arch/x86/insts/microldstop.hh"
44 #include "arch/x86/regs/misc.hh"
45 #include "arch/x86/regs/msr.hh"
46 #include "arch/x86/faults.hh"
47 #include "arch/x86/pagetable.hh"
48 #include "arch/x86/pagetable_walker.hh"
49 #include "arch/x86/tlb.hh"
50 #include "arch/x86/x86_traits.hh"
51 #include "base/bitfield.hh"
52 #include "base/trace.hh"
53 #include "cpu/base.hh"
54 #include "cpu/thread_context.hh"
55 #include "debug/TLB.hh"
56 #include "mem/packet_access.hh"
57 #include "mem/page_table.hh"
58 #include "mem/request.hh"
59 #include "sim/full_system.hh"
60 #include "sim/process.hh"
64 TLB::TLB(const Params
*p
) : BaseTLB(p
), configAddress(0), size(p
->size
),
68 fatal("TLBs must have a non-zero size.\n");
69 tlb
= new TlbEntry
[size
];
70 std::memset(tlb
, 0, sizeof(TlbEntry
) * size
);
72 for (int x
= 0; x
< size
; x
++) {
73 tlb
[x
].trieHandle
= NULL
;
74 freeList
.push_back(&tlb
[x
]);
84 // Find the entry with the lowest (and hence least recently updated)
88 for (unsigned i
= 1; i
< size
; i
++) {
89 if (tlb
[i
].lruSeq
< tlb
[lru
].lruSeq
)
93 assert(tlb
[lru
].trieHandle
);
94 trie
.remove(tlb
[lru
].trieHandle
);
95 tlb
[lru
].trieHandle
= NULL
;
96 freeList
.push_back(&tlb
[lru
]);
100 TLB::insert(Addr vpn
, TlbEntry
&entry
)
102 // If somebody beat us to it, just use that existing entry.
103 TlbEntry
*newEntry
= trie
.lookup(vpn
);
105 assert(newEntry
->vaddr
== vpn
);
109 if (freeList
.empty())
112 newEntry
= freeList
.front();
113 freeList
.pop_front();
116 newEntry
->lruSeq
= nextSeq();
117 newEntry
->vaddr
= vpn
;
118 newEntry
->trieHandle
=
119 trie
.insert(vpn
, TlbEntryTrie::MaxBits
- entry
.logBytes
, newEntry
);
124 TLB::lookup(Addr va
, bool update_lru
)
126 TlbEntry
*entry
= trie
.lookup(va
);
127 if (entry
&& update_lru
)
128 entry
->lruSeq
= nextSeq();
135 DPRINTF(TLB
, "Invalidating all entries.\n");
136 for (unsigned i
= 0; i
< size
; i
++) {
137 if (tlb
[i
].trieHandle
) {
138 trie
.remove(tlb
[i
].trieHandle
);
139 tlb
[i
].trieHandle
= NULL
;
140 freeList
.push_back(&tlb
[i
]);
146 TLB::setConfigAddress(uint32_t addr
)
148 configAddress
= addr
;
152 TLB::flushNonGlobal()
154 DPRINTF(TLB
, "Invalidating all non global entries.\n");
155 for (unsigned i
= 0; i
< size
; i
++) {
156 if (tlb
[i
].trieHandle
&& !tlb
[i
].global
) {
157 trie
.remove(tlb
[i
].trieHandle
);
158 tlb
[i
].trieHandle
= NULL
;
159 freeList
.push_back(&tlb
[i
]);
165 TLB::demapPage(Addr va
, uint64_t asn
)
167 TlbEntry
*entry
= trie
.lookup(va
);
169 trie
.remove(entry
->trieHandle
);
170 entry
->trieHandle
= NULL
;
171 freeList
.push_back(entry
);
176 TLB::translateInt(RequestPtr req
, ThreadContext
*tc
)
178 DPRINTF(TLB
, "Addresses references internal memory.\n");
179 Addr vaddr
= req
->getVaddr();
180 Addr prefix
= (vaddr
>> 3) & IntAddrPrefixMask
;
181 if (prefix
== IntAddrPrefixCPUID
) {
182 panic("CPUID memory space not yet implemented!\n");
183 } else if (prefix
== IntAddrPrefixMSR
) {
184 vaddr
= (vaddr
>> 3) & ~IntAddrPrefixMask
;
185 req
->setFlags(Request::MMAPPED_IPR
);
188 if (!msrAddrToIndex(regNum
, vaddr
))
189 return new GeneralProtection(0);
191 //The index is multiplied by the size of a MiscReg so that
192 //any memory dependence calculations will not see these as
194 req
->setPaddr((Addr
)regNum
* sizeof(MiscReg
));
196 } else if (prefix
== IntAddrPrefixIO
) {
197 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
198 // bitmap in the TSS.
200 Addr IOPort
= vaddr
& ~IntAddrPrefixMask
;
201 // Make sure the address fits in the expected 16 bit IO address
203 assert(!(IOPort
& ~0xFFFF));
204 if (IOPort
== 0xCF8 && req
->getSize() == 4) {
205 req
->setFlags(Request::MMAPPED_IPR
);
206 req
->setPaddr(MISCREG_PCI_CONFIG_ADDRESS
* sizeof(MiscReg
));
207 } else if ((IOPort
& ~mask(2)) == 0xCFC) {
208 req
->setFlags(Request::UNCACHEABLE
);
210 tc
->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS
);
211 if (bits(configAddress
, 31, 31)) {
212 req
->setPaddr(PhysAddrPrefixPciConfig
|
213 mbits(configAddress
, 30, 2) |
216 req
->setPaddr(PhysAddrPrefixIO
| IOPort
);
219 req
->setFlags(Request::UNCACHEABLE
);
220 req
->setPaddr(PhysAddrPrefixIO
| IOPort
);
224 panic("Access to unrecognized internal address space %#x.\n",
230 TLB::finalizePhysical(RequestPtr req
, ThreadContext
*tc
, Mode mode
) const
232 Addr paddr
= req
->getPaddr();
234 // Check for an access to the local APIC
236 LocalApicBase localApicBase
=
237 tc
->readMiscRegNoEffect(MISCREG_APIC_BASE
);
238 AddrRange
apicRange(localApicBase
.base
* PageBytes
,
239 (localApicBase
.base
+ 1) * PageBytes
- 1);
241 AddrRange
m5opRange(0xFFFF0000, 0xFFFFFFFF);
243 if (apicRange
.contains(paddr
)) {
244 // The Intel developer's manuals say the below restrictions apply,
245 // but the linux kernel, because of a compiler optimization, breaks
249 if (paddr & ((32/8) - 1))
250 return new GeneralProtection(0);
252 if (req->getSize() != (32/8))
253 return new GeneralProtection(0);
255 // Force the access to be uncacheable.
256 req
->setFlags(Request::UNCACHEABLE
);
257 req
->setPaddr(x86LocalAPICAddress(tc
->contextId(),
258 paddr
- apicRange
.start()));
259 } else if (m5opRange
.contains(paddr
)) {
260 req
->setFlags(Request::MMAPPED_IPR
);
261 req
->setPaddr(GenericISA::iprAddressPseudoInst(
271 TLB::translate(RequestPtr req
, ThreadContext
*tc
, Translation
*translation
,
272 Mode mode
, bool &delayedResponse
, bool timing
)
274 uint32_t flags
= req
->getFlags();
275 int seg
= flags
& SegmentFlagMask
;
276 bool storeCheck
= flags
& (StoreCheck
<< FlagShift
);
278 delayedResponse
= false;
280 // If this is true, we're dealing with a request to a non-memory address
282 if (seg
== SEGMENT_REG_MS
) {
283 return translateInt(req
, tc
);
286 Addr vaddr
= req
->getVaddr();
287 DPRINTF(TLB
, "Translating vaddr %#x.\n", vaddr
);
289 HandyM5Reg m5Reg
= tc
->readMiscRegNoEffect(MISCREG_M5_REG
);
291 // If protected mode has been enabled...
293 DPRINTF(TLB
, "In protected mode.\n");
294 // If we're not in 64-bit mode, do protection/limit checks
295 if (m5Reg
.mode
!= LongMode
) {
296 DPRINTF(TLB
, "Not in long mode. Checking segment protection.\n");
297 // Check for a NULL segment selector.
298 if (!(seg
== SEGMENT_REG_TSG
|| seg
== SYS_SEGMENT_REG_IDTR
||
299 seg
== SEGMENT_REG_HS
|| seg
== SEGMENT_REG_LS
)
300 && !tc
->readMiscRegNoEffect(MISCREG_SEG_SEL(seg
)))
301 return new GeneralProtection(0);
302 bool expandDown
= false;
303 SegAttr attr
= tc
->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg
));
304 if (seg
>= SEGMENT_REG_ES
&& seg
<= SEGMENT_REG_HS
) {
305 if (!attr
.writable
&& (mode
== Write
|| storeCheck
))
306 return new GeneralProtection(0);
307 if (!attr
.readable
&& mode
== Read
)
308 return new GeneralProtection(0);
309 expandDown
= attr
.expandDown
;
312 Addr base
= tc
->readMiscRegNoEffect(MISCREG_SEG_BASE(seg
));
313 Addr limit
= tc
->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg
));
314 bool sizeOverride
= (flags
& (AddrSizeFlagBit
<< FlagShift
));
315 unsigned logSize
= sizeOverride
? (unsigned)m5Reg
.altAddr
316 : (unsigned)m5Reg
.defAddr
;
317 int size
= (1 << logSize
) * 8;
318 Addr offset
= bits(vaddr
- base
, size
- 1, 0);
319 Addr endOffset
= offset
+ req
->getSize() - 1;
321 DPRINTF(TLB
, "Checking an expand down segment.\n");
322 warn_once("Expand down segments are untested.\n");
323 if (offset
<= limit
|| endOffset
<= limit
)
324 return new GeneralProtection(0);
326 if (offset
> limit
|| endOffset
> limit
)
327 return new GeneralProtection(0);
330 if (m5Reg
.submode
!= SixtyFourBitMode
||
331 (flags
& (AddrSizeFlagBit
<< FlagShift
)))
333 // If paging is enabled, do the translation.
335 DPRINTF(TLB
, "Paging enabled.\n");
336 // The vaddr already has the segment base applied.
337 TlbEntry
*entry
= lookup(vaddr
);
340 Fault fault
= walker
->start(tc
, translation
, req
, mode
);
341 if (timing
|| fault
!= NoFault
) {
342 // This gets ignored in atomic mode.
343 delayedResponse
= true;
346 entry
= lookup(vaddr
);
349 DPRINTF(TLB
, "Handling a TLB miss for "
350 "address %#x at pc %#x.\n",
351 vaddr
, tc
->instAddr());
353 Process
*p
= tc
->getProcessPtr();
355 bool success
= p
->pTable
->lookup(vaddr
, newEntry
);
356 if (!success
&& mode
!= Execute
) {
357 // Check if we just need to grow the stack.
358 if (p
->fixupStackFault(vaddr
)) {
359 // If we did, lookup the entry for the new page.
360 success
= p
->pTable
->lookup(vaddr
, newEntry
);
364 return new PageFault(vaddr
, true, mode
, true, false);
366 Addr alignedVaddr
= p
->pTable
->pageAlign(vaddr
);
367 DPRINTF(TLB
, "Mapping %#x to %#x\n", alignedVaddr
,
368 newEntry
.pageStart());
369 entry
= insert(alignedVaddr
, newEntry
);
371 DPRINTF(TLB
, "Miss was serviced.\n");
375 DPRINTF(TLB
, "Entry found with paddr %#x, "
376 "doing protection checks.\n", entry
->paddr
);
377 // Do paging protection checks.
378 bool inUser
= (m5Reg
.cpl
== 3 &&
379 !(flags
& (CPL0FlagBit
<< FlagShift
)));
380 CR0 cr0
= tc
->readMiscRegNoEffect(MISCREG_CR0
);
381 bool badWrite
= (!entry
->writable
&& (inUser
|| cr0
.wp
));
382 if ((inUser
&& !entry
->user
) || (mode
== Write
&& badWrite
)) {
383 // The page must have been present to get into the TLB in
384 // the first place. We'll assume the reserved bits are
385 // fine even though we're not checking them.
386 return new PageFault(vaddr
, true, mode
, inUser
, false);
388 if (storeCheck
&& badWrite
) {
389 // This would fault if this were a write, so return a page
390 // fault that reflects that happening.
391 return new PageFault(vaddr
, true, Write
, inUser
, false);
394 Addr paddr
= entry
->paddr
| (vaddr
& mask(entry
->logBytes
));
395 DPRINTF(TLB
, "Translated %#x -> %#x.\n", vaddr
, paddr
);
396 req
->setPaddr(paddr
);
397 if (entry
->uncacheable
)
398 req
->setFlags(Request::UNCACHEABLE
);
400 //Use the address which already has segmentation applied.
401 DPRINTF(TLB
, "Paging disabled.\n");
402 DPRINTF(TLB
, "Translated %#x -> %#x.\n", vaddr
, vaddr
);
403 req
->setPaddr(vaddr
);
407 DPRINTF(TLB
, "In real mode.\n");
408 DPRINTF(TLB
, "Translated %#x -> %#x.\n", vaddr
, vaddr
);
409 req
->setPaddr(vaddr
);
412 return finalizePhysical(req
, tc
, mode
);
416 TLB::translateAtomic(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
418 bool delayedResponse
;
419 return TLB::translate(req
, tc
, NULL
, mode
, delayedResponse
, false);
423 TLB::translateTiming(RequestPtr req
, ThreadContext
*tc
,
424 Translation
*translation
, Mode mode
)
426 bool delayedResponse
;
429 TLB::translate(req
, tc
, translation
, mode
, delayedResponse
, true);
430 if (!delayedResponse
)
431 translation
->finish(fault
, req
, tc
, mode
);
435 TLB::translateFunctional(RequestPtr req
, ThreadContext
*tc
, Mode mode
)
437 panic("Not implemented\n");
448 TLB::serialize(std::ostream
&os
)
450 // Only store the entries in use.
451 uint32_t _size
= size
- freeList
.size();
452 SERIALIZE_SCALAR(_size
);
453 SERIALIZE_SCALAR(lruSeq
);
457 for (uint32_t x
= 0; x
< size
; x
++) {
458 if (tlb
[x
].trieHandle
!= NULL
) {
459 os
<< "\n[" << csprintf("%s.Entry%d", name(), _count
) << "]\n";
460 tlb
[x
].serialize(os
);
467 TLB::unserialize(Checkpoint
*cp
, const std::string
§ion
)
469 // Do not allow to restore with a smaller tlb.
471 UNSERIALIZE_SCALAR(_size
);
473 fatal("TLB size less than the one in checkpoint!");
476 UNSERIALIZE_SCALAR(lruSeq
);
478 for (uint32_t x
= 0; x
< _size
; x
++) {
479 TlbEntry
*newEntry
= freeList
.front();
480 freeList
.pop_front();
482 newEntry
->unserialize(cp
, csprintf("%s.Entry%d", name(), x
));
483 newEntry
->trieHandle
= trie
.insert(newEntry
->vaddr
,
484 TlbEntryTrie::MaxBits
- newEntry
->logBytes
, newEntry
);
491 return &walker
->getMasterPort("port");
494 } // namespace X86ISA
497 X86TLBParams::create()
499 return new X86ISA::TLB(this);