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40 #ifndef __ARCH_X86_TLB_HH__
41 #define __ARCH_X86_TLB_HH__
47 #include "arch/x86/regs/segment.hh"
48 #include "arch/x86/pagetable.hh"
49 #include "base/trie.hh"
50 #include "mem/mem_object.hh"
51 #include "mem/request.hh"
52 #include "params/X86TLB.hh"
53 #include "sim/fault_fwd.hh"
54 #include "sim/sim_object.hh"
64 class TLB : public BaseTLB
69 typedef std::list<TlbEntry *> EntryList;
71 uint32_t configAddress;
75 typedef X86TLBParams Params;
78 TlbEntry *lookup(Addr va, bool update_lru = true);
80 void setConfigAddress(uint32_t addr);
84 EntryList::iterator lookupIt(Addr va, bool update_lru = true);
93 void flushNonGlobal();
95 void demapPage(Addr va, uint64_t asn);
108 Fault translateInt(RequestPtr req, ThreadContext *tc);
110 Fault translate(RequestPtr req, ThreadContext *tc,
111 Translation *translation, Mode mode,
112 bool &delayedResponse, bool timing);
124 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
125 void translateTiming(RequestPtr req, ThreadContext *tc,
126 Translation *translation, Mode mode);
127 /** Stub function for compilation support of CheckerCPU. x86 ISA does
128 * not support Checker model at the moment
130 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
132 TlbEntry * insert(Addr vpn, TlbEntry &entry);
135 virtual void serialize(std::ostream &os);
136 virtual void unserialize(Checkpoint *cp, const std::string §ion);
139 * Get the table walker master port. This is used for
140 * migrating port connections during a CPU takeOverFrom()
141 * call. For architectures that do not have a table walker,
142 * NULL is returned, hence the use of a pointer rather than a
143 * reference. For X86 this method will always return a valid
146 * @return A pointer to the walker master port
148 virtual BaseMasterPort *getMasterPort();
152 #endif // __ARCH_X86_TLB_HH__