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58 #ifndef __ARCH_X86_TLB_HH__
59 #define __ARCH_X86_TLB_HH__
65 #include "arch/x86/pagetable.hh"
66 #include "arch/x86/segmentregs.hh"
67 #include "config/full_system.hh"
68 #include "mem/mem_object.hh"
69 #include "mem/request.hh"
70 #include "params/X86DTB.hh"
71 #include "params/X86ITB.hh"
72 #include "sim/faults.hh"
74 #include "sim/sim_object.hh"
83 static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
87 class TLB : public BaseTLB
90 friend class FakeITLBFault;
91 friend class FakeDTLBFault;
93 typedef std::list<TlbEntry *> EntryList;
96 uint32_t configAddress;
104 typedef X86TLBParams Params;
105 TLB(const Params *p);
109 TlbEntry *lookup(Addr va, bool update_lru = true);
111 void setConfigAddress(uint32_t addr);
115 EntryList::iterator lookupIt(Addr va, bool update_lru = true);
122 void walk(ThreadContext * _tc, Addr vaddr, bool write, bool execute);
126 void invalidateAll();
128 void invalidateNonGlobal();
130 void demapPage(Addr va, uint64_t asn);
140 template<class TlbFault>
141 Fault translate(RequestPtr &req, ThreadContext *tc,
142 bool write, bool execute);
146 void insert(Addr vpn, TlbEntry &entry);
149 virtual void serialize(std::ostream &os);
150 virtual void unserialize(Checkpoint *cp, const std::string §ion);
153 class ITB : public TLB
156 typedef X86ITBParams Params;
157 ITB(const Params *p) : TLB(p)
162 Fault translate(RequestPtr &req, ThreadContext *tc);
167 class DTB : public TLB
170 typedef X86DTBParams Params;
171 DTB(const Params *p) : TLB(p)
175 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
177 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
178 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
182 virtual void serialize(std::ostream &os);
183 virtual void unserialize(Checkpoint *cp, const std::string §ion);
187 #endif // __ARCH_X86_TLB_HH__