src/arch/x86/tlb.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  */
  39
  40 #ifndef __ARCH_X86_TLB_HH__
  41 #define __ARCH_X86_TLB_HH__
  42
  43 #include <list>
  44 #include <string>
  45 #include <vector>
  46
  47 #include "arch/x86/regs/segment.hh"
  48 #include "arch/x86/pagetable.hh"
  49 #include "base/trie.hh"
  50 #include "mem/mem_object.hh"
  51 #include "mem/request.hh"
  52 #include "params/X86TLB.hh"
  53 #include "sim/fault_fwd.hh"
  54 #include "sim/sim_object.hh"
  55 #include "sim/tlb.hh"
  56
  57 class ThreadContext;
  58 class Packet;
  59
  60 namespace X86ISA
  61 {
  62     class Walker;
  63
  64     class TLB : public BaseTLB
  65     {
  66       protected:
  67         friend class Walker;
  68
  69         typedef std::list<TlbEntry *> EntryList;
  70
  71         uint32_t configAddress;
  72
  73       public:
  74
  75         typedef X86TLBParams Params;
  76         TLB(const Params *p);
  77
  78         void dumpAll();
  79
  80         TlbEntry *lookup(Addr va, bool update_lru = true);
  81
  82         void setConfigAddress(uint32_t addr);
  83
  84       protected:
  85
  86         EntryList::iterator lookupIt(Addr va, bool update_lru = true);
  87
  88         Walker * walker;
  89
  90       public:
  91         Walker *getWalker();
  92
  93         void invalidateAll();
  94
  95         void invalidateNonGlobal();
  96
  97         void demapPage(Addr va, uint64_t asn);
  98
  99       protected:
 100         int size;
 101
 102         TlbEntry * tlb;
 103
 104         EntryList freeList;
 105         EntryList entryList;
 106
 107         TlbEntryTrie trie;
 108         uint64_t lruSeq;
 109
 110         Fault translateInt(RequestPtr req, ThreadContext *tc);
 111
 112         Fault translate(RequestPtr req, ThreadContext *tc,
 113                 Translation *translation, Mode mode,
 114                 bool &delayedResponse, bool timing);
 115
 116       public:
 117
 118         void evictLRU();
 119
 120         uint64_t
 121         nextSeq()
 122         {
 123             return ++lruSeq;
 124         }
 125
 126         Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
 127         void translateTiming(RequestPtr req, ThreadContext *tc,
 128                 Translation *translation, Mode mode);
 129         /** Stub function for compilation support of CheckerCPU. x86 ISA does
 130          *  not support Checker model at the moment
 131          */
 132         Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
 133
 134         TlbEntry * insert(Addr vpn, TlbEntry &entry);
 135
 136         // Checkpointing
 137         virtual void serialize(std::ostream &os);
 138         virtual void unserialize(Checkpoint *cp, const std::string &section);
 139
 140         /**
 141          * Get the table walker master port. This is used for
 142          * migrating port connections during a CPU takeOverFrom()
 143          * call. For architectures that do not have a table walker,
 144          * NULL is returned, hence the use of a pointer rather than a
 145          * reference. For X86 this method will always return a valid
 146          * port pointer.
 147          *
 148          * @return A pointer to the walker master port
 149          */
 150         virtual BaseMasterPort *getMasterPort();
 151     };
 152 }
 153
 154 #endif // __ARCH_X86_TLB_HH__