2 * Copyright (c) 2007 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #ifndef __ARCH_X86_TLB_HH__
41 #define __ARCH_X86_TLB_HH__
47 #include "arch/generic/tlb.hh"
48 #include "arch/x86/regs/segment.hh"
49 #include "arch/x86/pagetable.hh"
50 #include "base/trie.hh"
51 #include "mem/mem_object.hh"
52 #include "mem/request.hh"
53 #include "params/X86TLB.hh"
54 #include "sim/sim_object.hh"
63 class TLB : public BaseTLB
68 typedef std::list<TlbEntry *> EntryList;
70 uint32_t configAddress;
74 typedef X86TLBParams Params;
77 void takeOverFrom(BaseTLB *otlb) {}
79 TlbEntry *lookup(Addr va, bool update_lru = true);
81 void setConfigAddress(uint32_t addr);
85 EntryList::iterator lookupIt(Addr va, bool update_lru = true);
94 void flushNonGlobal();
96 void demapPage(Addr va, uint64_t asn);
101 std::vector<TlbEntry> tlb;
108 Fault translateInt(RequestPtr req, ThreadContext *tc);
110 Fault translate(RequestPtr req, ThreadContext *tc,
111 Translation *translation, Mode mode,
112 bool &delayedResponse, bool timing);
124 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
125 void translateTiming(RequestPtr req, ThreadContext *tc,
126 Translation *translation, Mode mode);
127 /** Stub function for compilation support of CheckerCPU. x86 ISA does
128 * not support Checker model at the moment
130 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
133 * Do post-translation physical address finalization.
135 * Some addresses, for example requests going to the APIC,
136 * need post-translation updates. Such physical addresses are
137 * remapped into a "magic" part of the physical address space
140 * @param req Request to updated in-place.
141 * @param tc Thread context that created the request.
142 * @param mode Request type (read/write/execute).
143 * @return A fault on failure, NoFault otherwise.
145 Fault finalizePhysical(RequestPtr req, ThreadContext *tc,
148 TlbEntry * insert(Addr vpn, TlbEntry &entry);
151 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
152 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
155 * Get the table walker master port. This is used for
156 * migrating port connections during a CPU takeOverFrom()
157 * call. For architectures that do not have a table walker,
158 * NULL is returned, hence the use of a pointer rather than a
159 * reference. For X86 this method will always return a valid
162 * @return A pointer to the walker master port
164 virtual BaseMasterPort *getMasterPort();
168 #endif // __ARCH_X86_TLB_HH__