src/arch/x86/types.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  */
  39
  40 #ifndef __ARCH_X86_TYPES_HH__
  41 #define __ARCH_X86_TYPES_HH__
  42
  43 #include <iostream>
  44
  45 #include "base/bitunion.hh"
  46 #include "base/cprintf.hh"
  47 #include "base/hashmap.hh"
  48 #include "base/types.hh"
  49 #include "sim/serialize.hh"
  50
  51 namespace X86ISA
  52 {
  53     //This really determines how many bytes are passed to the predecoder.
  54     typedef uint64_t MachInst;
  55
  56     enum Prefixes {
  57         NoOverride,
  58         ESOverride,
  59         CSOverride,
  60         SSOverride,
  61         DSOverride,
  62         FSOverride,
  63         GSOverride,
  64         RexPrefix,
  65         OperandSizeOverride,
  66         AddressSizeOverride,
  67         Lock,
  68         Rep,
  69         Repne
  70     };
  71
  72     BitUnion8(LegacyPrefixVector)
  73         Bitfield<7, 4> decodeVal;
  74         Bitfield<7> repne;
  75         Bitfield<6> rep;
  76         Bitfield<5> lock;
  77         Bitfield<4> op;
  78         Bitfield<3> addr;
  79         //There can be only one segment override, so they share the
  80         //first 3 bits in the legacyPrefixes bitfield.
  81         Bitfield<2,0> seg;
  82     EndBitUnion(LegacyPrefixVector)
  83
  84     BitUnion8(ModRM)
  85         Bitfield<7,6> mod;
  86         Bitfield<5,3> reg;
  87         Bitfield<2,0> rm;
  88     EndBitUnion(ModRM)
  89
  90     BitUnion8(Sib)
  91         Bitfield<7,6> scale;
  92         Bitfield<5,3> index;
  93         Bitfield<2,0> base;
  94     EndBitUnion(Sib)
  95
  96     BitUnion8(Rex)
  97         //This bit doesn't mean anything according to the ISA, but in
  98         //this implementation, it being set means an REX prefix was present.
  99         Bitfield<6> present;
 100         Bitfield<3> w;
 101         Bitfield<2> r;
 102         Bitfield<1> x;
 103         Bitfield<0> b;
 104     EndBitUnion(Rex)
 105
 106     BitUnion8(Opcode)
 107         Bitfield<7,3> top5;
 108         Bitfield<2,0> bottom3;
 109     EndBitUnion(Opcode)
 110
 111     BitUnion8(OperatingMode)
 112         Bitfield<3> mode;
 113         Bitfield<2,0> submode;
 114     EndBitUnion(OperatingMode)
 115
 116     enum X86Mode {
 117         LongMode,
 118         LegacyMode
 119     };
 120
 121     enum X86SubMode {
 122         SixtyFourBitMode,
 123         CompatabilityMode,
 124         ProtectedMode,
 125         Virtual8086Mode,
 126         RealMode
 127     };
 128
 129     //The intermediate structure the x86 predecoder returns.
 130     struct ExtMachInst
 131     {
 132         //Prefixes
 133         LegacyPrefixVector legacy;
 134         Rex rex;
 135         //This holds all of the bytes of the opcode
 136         struct
 137         {
 138             //The number of bytes in this opcode. Right now, we ignore that
 139             //this can be 3 in some cases
 140             uint8_t num;
 141             //The first byte detected in a 2+ byte opcode. Should be 0xF0.
 142             uint8_t prefixA;
 143             //The second byte detected in a 3+ byte opcode. Could be 0x38-0x3F
 144             //for some SSE instructions. 3dNow! instructions are handled as
 145             //two byte opcodes and then split out further by the immediate
 146             //byte.
 147             uint8_t prefixB;
 148             //The main opcode byte. The highest addressed byte in the opcode.
 149             Opcode op;
 150         } opcode;
 151         //Modifier bytes
 152         ModRM modRM;
 153         Sib sib;
 154         //Immediate fields
 155         uint64_t immediate;
 156         uint64_t displacement;
 157
 158         //The effective operand size.
 159         uint8_t opSize;
 160         //The effective address size.
 161         uint8_t addrSize;
 162         //The effective stack size.
 163         uint8_t stackSize;
 164         //The size of the displacement
 165         uint8_t dispSize;
 166
 167         //Mode information
 168         OperatingMode mode;
 169     };
 170
 171     inline static std::ostream &
 172         operator << (std::ostream & os, const ExtMachInst & emi)
 173     {
 174         ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
 175                      "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
 176                            "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
 177                      "modRM = %#x,\n\tsib = %#x,\n\t"
 178                      "immediate = %#x,\n\tdisplacement = %#x\n\t"
 179                      "dispSize = %d}\n",
 180                      (uint8_t)emi.legacy, (uint8_t)emi.rex,
 181                      emi.opcode.num, (uint8_t)emi.opcode.op,
 182                      emi.opcode.prefixA, emi.opcode.prefixB,
 183                      (uint8_t)emi.modRM, (uint8_t)emi.sib,
 184                      emi.immediate, emi.displacement, emi.dispSize);
 185         return os;
 186     }
 187
 188     inline static bool
 189         operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
 190     {
 191         if(emi1.legacy != emi2.legacy)
 192             return false;
 193         if(emi1.rex != emi2.rex)
 194             return false;
 195         if(emi1.opcode.num != emi2.opcode.num)
 196             return false;
 197         if(emi1.opcode.op != emi2.opcode.op)
 198             return false;
 199         if(emi1.opcode.prefixA != emi2.opcode.prefixA)
 200             return false;
 201         if(emi1.opcode.prefixB != emi2.opcode.prefixB)
 202             return false;
 203         if(emi1.modRM != emi2.modRM)
 204             return false;
 205         if(emi1.sib != emi2.sib)
 206             return false;
 207         if(emi1.immediate != emi2.immediate)
 208             return false;
 209         if(emi1.displacement != emi2.displacement)
 210             return false;
 211         if(emi1.mode != emi2.mode)
 212             return false;
 213         if(emi1.opSize != emi2.opSize)
 214             return false;
 215         if(emi1.addrSize != emi2.addrSize)
 216             return false;
 217         if(emi1.stackSize != emi2.stackSize)
 218             return false;
 219         if(emi1.dispSize != emi2.dispSize)
 220             return false;
 221         return true;
 222     }
 223
 224     struct CoreSpecific {
 225         int core_type;
 226     };
 227 };
 228
 229 namespace __hash_namespace {
 230     template<>
 231     struct hash<X86ISA::ExtMachInst> {
 232         size_t operator()(const X86ISA::ExtMachInst &emi) const {
 233             return (((uint64_t)emi.legacy << 56) |
 234                     ((uint64_t)emi.rex  << 48) |
 235                     ((uint64_t)emi.modRM << 40) |
 236                     ((uint64_t)emi.sib << 32) |
 237                     ((uint64_t)emi.opcode.num << 24) |
 238                     ((uint64_t)emi.opcode.prefixA << 16) |
 239                     ((uint64_t)emi.opcode.prefixB << 8) |
 240                     ((uint64_t)emi.opcode.op)) ^
 241                     emi.immediate ^ emi.displacement ^
 242                     emi.mode ^
 243                     emi.opSize ^ emi.addrSize ^
 244                     emi.stackSize ^ emi.dispSize;
 245         };
 246     };
 247 }
 248
 249 // These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
 250 // and UNSERIALIZE_SCALAR.
 251 template <>
 252 void
 253 paramOut(std::ostream &os, const std::string &name,
 254          const X86ISA::ExtMachInst &machInst);
 255 template <>
 256 void
 257 paramIn(Checkpoint *cp, const std::string &section,
 258         const std::string &name, X86ISA::ExtMachInst &machInst);
 259
 260 #endif // __ARCH_X86_TYPES_HH__