src/arch/x86/types.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  */
  39
  40 #ifndef __ARCH_X86_TYPES_HH__
  41 #define __ARCH_X86_TYPES_HH__
  42
  43 #include <iostream>
  44
  45 #include "base/bitunion.hh"
  46 #include "base/cprintf.hh"
  47 #include "base/types.hh"
  48 #include "sim/serialize.hh"
  49
  50 namespace X86ISA
  51 {
  52     //This really determines how many bytes are passed to the predecoder.
  53     typedef uint64_t MachInst;
  54
  55     enum Prefixes {
  56         NoOverride,
  57         ESOverride,
  58         CSOverride,
  59         SSOverride,
  60         DSOverride,
  61         FSOverride,
  62         GSOverride,
  63         RexPrefix,
  64         OperandSizeOverride,
  65         AddressSizeOverride,
  66         Lock,
  67         Rep,
  68         Repne
  69     };
  70
  71     BitUnion8(LegacyPrefixVector)
  72         Bitfield<7, 4> decodeVal;
  73         Bitfield<7> repne;
  74         Bitfield<6> rep;
  75         Bitfield<5> lock;
  76         Bitfield<4> op;
  77         Bitfield<3> addr;
  78         //There can be only one segment override, so they share the
  79         //first 3 bits in the legacyPrefixes bitfield.
  80         Bitfield<2,0> seg;
  81     EndBitUnion(LegacyPrefixVector)
  82
  83     BitUnion8(ModRM)
  84         Bitfield<7,6> mod;
  85         Bitfield<5,3> reg;
  86         Bitfield<2,0> rm;
  87     EndBitUnion(ModRM)
  88
  89     BitUnion8(Sib)
  90         Bitfield<7,6> scale;
  91         Bitfield<5,3> index;
  92         Bitfield<2,0> base;
  93     EndBitUnion(Sib)
  94
  95     BitUnion8(Rex)
  96         //This bit doesn't mean anything according to the ISA, but in
  97         //this implementation, it being set means an REX prefix was present.
  98         Bitfield<6> present;
  99         Bitfield<3> w;
 100         Bitfield<2> r;
 101         Bitfield<1> x;
 102         Bitfield<0> b;
 103     EndBitUnion(Rex)
 104
 105     BitUnion8(Opcode)
 106         Bitfield<7,3> top5;
 107         Bitfield<2,0> bottom3;
 108     EndBitUnion(Opcode)
 109
 110     BitUnion8(OperatingMode)
 111         Bitfield<3> mode;
 112         Bitfield<2,0> submode;
 113     EndBitUnion(OperatingMode)
 114
 115     enum X86Mode {
 116         LongMode,
 117         LegacyMode
 118     };
 119
 120     enum X86SubMode {
 121         SixtyFourBitMode,
 122         CompatabilityMode,
 123         ProtectedMode,
 124         Virtual8086Mode,
 125         RealMode
 126     };
 127
 128     //The intermediate structure the x86 predecoder returns.
 129     struct ExtMachInst
 130     {
 131         //Prefixes
 132         LegacyPrefixVector legacy;
 133         Rex rex;
 134         //This holds all of the bytes of the opcode
 135         struct
 136         {
 137             //The number of bytes in this opcode. Right now, we ignore that
 138             //this can be 3 in some cases
 139             uint8_t num;
 140             //The first byte detected in a 2+ byte opcode. Should be 0xF0.
 141             uint8_t prefixA;
 142             //The second byte detected in a 3+ byte opcode. Could be 0x38-0x3F
 143             //for some SSE instructions. 3dNow! instructions are handled as
 144             //two byte opcodes and then split out further by the immediate
 145             //byte.
 146             uint8_t prefixB;
 147             //The main opcode byte. The highest addressed byte in the opcode.
 148             Opcode op;
 149         } opcode;
 150         //Modifier bytes
 151         ModRM modRM;
 152         Sib sib;
 153         //Immediate fields
 154         uint64_t immediate;
 155         uint64_t displacement;
 156
 157         //The effective operand size.
 158         uint8_t opSize;
 159         //The effective address size.
 160         uint8_t addrSize;
 161         //The effective stack size.
 162         uint8_t stackSize;
 163         //The size of the displacement
 164         uint8_t dispSize;
 165
 166         //Mode information
 167         OperatingMode mode;
 168     };
 169
 170     inline static std::ostream &
 171         operator << (std::ostream & os, const ExtMachInst & emi)
 172     {
 173         ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
 174                      "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
 175                            "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
 176                      "modRM = %#x,\n\tsib = %#x,\n\t"
 177                      "immediate = %#x,\n\tdisplacement = %#x\n\t"
 178                      "dispSize = %d}\n",
 179                      (uint8_t)emi.legacy, (uint8_t)emi.rex,
 180                      emi.opcode.num, (uint8_t)emi.opcode.op,
 181                      emi.opcode.prefixA, emi.opcode.prefixB,
 182                      (uint8_t)emi.modRM, (uint8_t)emi.sib,
 183                      emi.immediate, emi.displacement, emi.dispSize);
 184         return os;
 185     }
 186
 187     inline static bool
 188         operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
 189     {
 190         if(emi1.legacy != emi2.legacy)
 191             return false;
 192         if(emi1.rex != emi2.rex)
 193             return false;
 194         if(emi1.opcode.num != emi2.opcode.num)
 195             return false;
 196         if(emi1.opcode.op != emi2.opcode.op)
 197             return false;
 198         if(emi1.opcode.prefixA != emi2.opcode.prefixA)
 199             return false;
 200         if(emi1.opcode.prefixB != emi2.opcode.prefixB)
 201             return false;
 202         if(emi1.modRM != emi2.modRM)
 203             return false;
 204         if(emi1.sib != emi2.sib)
 205             return false;
 206         if(emi1.immediate != emi2.immediate)
 207             return false;
 208         if(emi1.displacement != emi2.displacement)
 209             return false;
 210         if(emi1.mode != emi2.mode)
 211             return false;
 212         if(emi1.opSize != emi2.opSize)
 213             return false;
 214         if(emi1.addrSize != emi2.addrSize)
 215             return false;
 216         if(emi1.stackSize != emi2.stackSize)
 217             return false;
 218         if(emi1.dispSize != emi2.dispSize)
 219             return false;
 220         return true;
 221     }
 222
 223     struct CoreSpecific {
 224         int core_type;
 225     };
 226 };
 227
 228 // These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
 229 // and UNSERIALIZE_SCALAR.
 230 template <>
 231 void
 232 paramOut(std::ostream &os, const std::string &name,
 233          const X86ISA::ExtMachInst &machInst);
 234 template <>
 235 void
 236 paramIn(Checkpoint *cp, const std::string &section,
 237         const std::string &name, X86ISA::ExtMachInst &machInst);
 238
 239 #endif // __ARCH_X86_TYPES_HH__