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40 #ifndef __ARCH_X86_TYPES_HH__
41 #define __ARCH_X86_TYPES_HH__
45 #include "arch/generic/types.hh"
46 #include "base/bitunion.hh"
47 #include "base/cprintf.hh"
48 #include "base/hashmap.hh"
49 #include "base/types.hh"
50 #include "sim/serialize.hh"
54 //This really determines how many bytes are passed to the predecoder.
55 typedef uint64_t MachInst;
73 BitUnion8(LegacyPrefixVector)
74 Bitfield<7, 4> decodeVal;
80 //There can be only one segment override, so they share the
81 //first 3 bits in the legacyPrefixes bitfield.
83 EndBitUnion(LegacyPrefixVector)
98 //This bit doesn't mean anything according to the ISA, but in
99 //this implementation, it being set means an REX prefix was present.
109 Bitfield<2,0> bottom3;
112 BitUnion8(OperatingMode)
114 Bitfield<2,0> submode;
115 EndBitUnion(OperatingMode)
130 //The intermediate structure the x86 predecoder returns.
134 LegacyPrefixVector legacy;
136 //This holds all of the bytes of the opcode
139 //The number of bytes in this opcode. Right now, we ignore that
140 //this can be 3 in some cases
142 //The first byte detected in a 2+ byte opcode. Should be 0xF0.
144 //The second byte detected in a 3+ byte opcode. Could be 0x38-0x3F
145 //for some SSE instructions. 3dNow! instructions are handled as
146 //two byte opcodes and then split out further by the immediate
149 //The main opcode byte. The highest addressed byte in the opcode.
157 uint64_t displacement;
159 //The effective operand size.
161 //The effective address size.
163 //The effective stack size.
165 //The size of the displacement
172 inline static std::ostream &
173 operator << (std::ostream & os, const ExtMachInst & emi)
175 ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
176 "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
177 "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
178 "modRM = %#x,\n\tsib = %#x,\n\t"
179 "immediate = %#x,\n\tdisplacement = %#x\n\t"
181 (uint8_t)emi.legacy, (uint8_t)emi.rex,
182 emi.opcode.num, (uint8_t)emi.opcode.op,
183 emi.opcode.prefixA, emi.opcode.prefixB,
184 (uint8_t)emi.modRM, (uint8_t)emi.sib,
185 emi.immediate, emi.displacement, emi.dispSize);
190 operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
192 if(emi1.legacy != emi2.legacy)
194 if(emi1.rex != emi2.rex)
196 if(emi1.opcode.num != emi2.opcode.num)
198 if(emi1.opcode.op != emi2.opcode.op)
200 if(emi1.opcode.prefixA != emi2.opcode.prefixA)
202 if(emi1.opcode.prefixB != emi2.opcode.prefixB)
204 if(emi1.modRM != emi2.modRM)
206 if(emi1.sib != emi2.sib)
208 if(emi1.immediate != emi2.immediate)
210 if(emi1.displacement != emi2.displacement)
212 if(emi1.mode != emi2.mode)
214 if(emi1.opSize != emi2.opSize)
216 if(emi1.addrSize != emi2.addrSize)
218 if(emi1.stackSize != emi2.stackSize)
220 if(emi1.dispSize != emi2.dispSize)
225 class PCState : public GenericISA::UPCState<MachInst>
228 typedef GenericISA::UPCState<MachInst> Base;
241 PCState(Addr val) { set(val); }
243 uint8_t size() const { return _size; }
244 void size(uint8_t newSize) { _size = newSize; }
249 return this->npc() != this->pc() + size();
267 serialize(std::ostream &os)
270 SERIALIZE_SCALAR(_size);
274 unserialize(Checkpoint *cp, const std::string §ion)
276 Base::unserialize(cp, section);
277 UNSERIALIZE_SCALAR(_size);
283 __hash_namespace_begin
285 struct hash<X86ISA::ExtMachInst> {
286 size_t operator()(const X86ISA::ExtMachInst &emi) const {
287 return (((uint64_t)emi.legacy << 56) |
288 ((uint64_t)emi.rex << 48) |
289 ((uint64_t)emi.modRM << 40) |
290 ((uint64_t)emi.sib << 32) |
291 ((uint64_t)emi.opcode.num << 24) |
292 ((uint64_t)emi.opcode.prefixA << 16) |
293 ((uint64_t)emi.opcode.prefixB << 8) |
294 ((uint64_t)emi.opcode.op)) ^
295 emi.immediate ^ emi.displacement ^
297 emi.opSize ^ emi.addrSize ^
298 emi.stackSize ^ emi.dispSize;
303 // These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
304 // and UNSERIALIZE_SCALAR.
307 paramOut(std::ostream &os, const std::string &name,
308 const X86ISA::ExtMachInst &machInst);
311 paramIn(Checkpoint *cp, const std::string §ion,
312 const std::string &name, X86ISA::ExtMachInst &machInst);
314 #endif // __ARCH_X86_TYPES_HH__