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58 #ifndef __ARCH_X86_TYPES_HH__
59 #define __ARCH_X86_TYPES_HH__
63 #include "base/bitunion.hh"
64 #include "base/cprintf.hh"
65 #include "base/types.hh"
69 //This really determines how many bytes are passed to the predecoder.
70 typedef uint64_t MachInst;
88 BitUnion8(LegacyPrefixVector)
89 Bitfield<7, 4> decodeVal;
95 //There can be only one segment override, so they share the
96 //first 3 bits in the legacyPrefixes bitfield.
98 EndBitUnion(LegacyPrefixVector)
113 //This bit doesn't mean anything according to the ISA, but in
114 //this implementation, it being set means an REX prefix was present.
124 Bitfield<2,0> bottom3;
127 BitUnion8(OperatingMode)
129 Bitfield<2,0> submode;
130 EndBitUnion(OperatingMode)
145 //The intermediate structure the x86 predecoder returns.
149 LegacyPrefixVector legacy;
151 //This holds all of the bytes of the opcode
154 //The number of bytes in this opcode. Right now, we ignore that
155 //this can be 3 in some cases
157 //The first byte detected in a 2+ byte opcode. Should be 0xF0.
159 //The second byte detected in a 3+ byte opcode. Could be 0x38-0x3F
160 //for some SSE instructions. 3dNow! instructions are handled as
161 //two byte opcodes and then split out further by the immediate
164 //The main opcode byte. The highest addressed byte in the opcode.
172 uint64_t displacement;
174 //The effective operand size.
176 //The effective address size.
178 //The effective stack size.
180 //The size of the displacement
187 inline static std::ostream &
188 operator << (std::ostream & os, const ExtMachInst & emi)
190 ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
191 "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
192 "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
193 "modRM = %#x,\n\tsib = %#x,\n\t"
194 "immediate = %#x,\n\tdisplacement = %#x\n\t"
196 (uint8_t)emi.legacy, (uint8_t)emi.rex,
197 emi.opcode.num, (uint8_t)emi.opcode.op,
198 emi.opcode.prefixA, emi.opcode.prefixB,
199 (uint8_t)emi.modRM, (uint8_t)emi.sib,
200 emi.immediate, emi.displacement, emi.dispSize);
205 operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
207 if(emi1.legacy != emi2.legacy)
209 if(emi1.rex != emi2.rex)
211 if(emi1.opcode.num != emi2.opcode.num)
213 if(emi1.opcode.op != emi2.opcode.op)
215 if(emi1.opcode.prefixA != emi2.opcode.prefixA)
217 if(emi1.opcode.prefixB != emi2.opcode.prefixB)
219 if(emi1.modRM != emi2.modRM)
221 if(emi1.sib != emi2.sib)
223 if(emi1.immediate != emi2.immediate)
225 if(emi1.displacement != emi2.displacement)
227 if(emi1.mode != emi2.mode)
229 if(emi1.opSize != emi2.opSize)
231 if(emi1.addrSize != emi2.addrSize)
233 if(emi1.stackSize != emi2.stackSize)
235 if(emi1.dispSize != emi2.dispSize)
240 struct CoreSpecific {
245 #endif // __ARCH_X86_TYPES_HH__