src/arch/x86/types.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
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  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
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  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_TYPES_HH__
  59 #define __ARCH_X86_TYPES_HH__
  60
  61 #include <iostream>
  62
  63 #include "base/bitunion.hh"
  64 #include "base/cprintf.hh"
  65 #include "base/types.hh"
  66
  67 namespace X86ISA
  68 {
  69     //This really determines how many bytes are passed to the predecoder.
  70     typedef uint64_t MachInst;
  71
  72     enum Prefixes {
  73         NoOverride,
  74         ESOverride,
  75         CSOverride,
  76         SSOverride,
  77         DSOverride,
  78         FSOverride,
  79         GSOverride,
  80         RexPrefix,
  81         OperandSizeOverride,
  82         AddressSizeOverride,
  83         Lock,
  84         Rep,
  85         Repne
  86     };
  87
  88     BitUnion8(LegacyPrefixVector)
  89         Bitfield<7, 4> decodeVal;
  90         Bitfield<7> repne;
  91         Bitfield<6> rep;
  92         Bitfield<5> lock;
  93         Bitfield<4> op;
  94         Bitfield<3> addr;
  95         //There can be only one segment override, so they share the
  96         //first 3 bits in the legacyPrefixes bitfield.
  97         Bitfield<2,0> seg;
  98     EndBitUnion(LegacyPrefixVector)
  99
 100     BitUnion8(ModRM)
 101         Bitfield<7,6> mod;
 102         Bitfield<5,3> reg;
 103         Bitfield<2,0> rm;
 104     EndBitUnion(ModRM)
 105
 106     BitUnion8(Sib)
 107         Bitfield<7,6> scale;
 108         Bitfield<5,3> index;
 109         Bitfield<2,0> base;
 110     EndBitUnion(Sib)
 111
 112     BitUnion8(Rex)
 113         //This bit doesn't mean anything according to the ISA, but in
 114         //this implementation, it being set means an REX prefix was present.
 115         Bitfield<6> present;
 116         Bitfield<3> w;
 117         Bitfield<2> r;
 118         Bitfield<1> x;
 119         Bitfield<0> b;
 120     EndBitUnion(Rex)
 121
 122     BitUnion8(Opcode)
 123         Bitfield<7,3> top5;
 124         Bitfield<2,0> bottom3;
 125     EndBitUnion(Opcode)
 126
 127     BitUnion8(OperatingMode)
 128         Bitfield<3> mode;
 129         Bitfield<2,0> submode;
 130     EndBitUnion(OperatingMode)
 131
 132     enum X86Mode {
 133         LongMode,
 134         LegacyMode
 135     };
 136
 137     enum X86SubMode {
 138         SixtyFourBitMode,
 139         CompatabilityMode,
 140         ProtectedMode,
 141         Virtual8086Mode,
 142         RealMode
 143     };
 144
 145     //The intermediate structure the x86 predecoder returns.
 146     struct ExtMachInst
 147     {
 148         //Prefixes
 149         LegacyPrefixVector legacy;
 150         Rex rex;
 151         //This holds all of the bytes of the opcode
 152         struct
 153         {
 154             //The number of bytes in this opcode. Right now, we ignore that
 155             //this can be 3 in some cases
 156             uint8_t num;
 157             //The first byte detected in a 2+ byte opcode. Should be 0xF0.
 158             uint8_t prefixA;
 159             //The second byte detected in a 3+ byte opcode. Could be 0x38-0x3F
 160             //for some SSE instructions. 3dNow! instructions are handled as
 161             //two byte opcodes and then split out further by the immediate
 162             //byte.
 163             uint8_t prefixB;
 164             //The main opcode byte. The highest addressed byte in the opcode.
 165             Opcode op;
 166         } opcode;
 167         //Modifier bytes
 168         ModRM modRM;
 169         Sib sib;
 170         //Immediate fields
 171         uint64_t immediate;
 172         uint64_t displacement;
 173
 174         //The effective operand size.
 175         uint8_t opSize;
 176         //The effective address size.
 177         uint8_t addrSize;
 178         //The effective stack size.
 179         uint8_t stackSize;
 180         //The size of the displacement
 181         uint8_t dispSize;
 182
 183         //Mode information
 184         OperatingMode mode;
 185     };
 186
 187     inline static std::ostream &
 188         operator << (std::ostream & os, const ExtMachInst & emi)
 189     {
 190         ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
 191                      "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
 192                            "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
 193                      "modRM = %#x,\n\tsib = %#x,\n\t"
 194                      "immediate = %#x,\n\tdisplacement = %#x\n\t"
 195                      "dispSize = %d}\n",
 196                      (uint8_t)emi.legacy, (uint8_t)emi.rex,
 197                      emi.opcode.num, (uint8_t)emi.opcode.op,
 198                      emi.opcode.prefixA, emi.opcode.prefixB,
 199                      (uint8_t)emi.modRM, (uint8_t)emi.sib,
 200                      emi.immediate, emi.displacement, emi.dispSize);
 201         return os;
 202     }
 203
 204     inline static bool
 205         operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
 206     {
 207         if(emi1.legacy != emi2.legacy)
 208             return false;
 209         if(emi1.rex != emi2.rex)
 210             return false;
 211         if(emi1.opcode.num != emi2.opcode.num)
 212             return false;
 213         if(emi1.opcode.op != emi2.opcode.op)
 214             return false;
 215         if(emi1.opcode.prefixA != emi2.opcode.prefixA)
 216             return false;
 217         if(emi1.opcode.prefixB != emi2.opcode.prefixB)
 218             return false;
 219         if(emi1.modRM != emi2.modRM)
 220             return false;
 221         if(emi1.sib != emi2.sib)
 222             return false;
 223         if(emi1.immediate != emi2.immediate)
 224             return false;
 225         if(emi1.displacement != emi2.displacement)
 226             return false;
 227         if(emi1.mode != emi2.mode)
 228             return false;
 229         if(emi1.opSize != emi2.opSize)
 230             return false;
 231         if(emi1.addrSize != emi2.addrSize)
 232             return false;
 233         if(emi1.stackSize != emi2.stackSize)
 234             return false;
 235         if(emi1.dispSize != emi2.dispSize)
 236             return false;
 237         return true;
 238     }
 239
 240     struct CoreSpecific {
 241         int core_type;
 242     };
 243 };
 244
 245 #endif // __ARCH_X86_TYPES_HH__