src/arch/x86/types.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Gabe Black
  38  */
  39
  40 #ifndef __ARCH_X86_TYPES_HH__
  41 #define __ARCH_X86_TYPES_HH__
  42
  43 #include <iostream>
  44
  45 #include "base/bitunion.hh"
  46 #include "base/cprintf.hh"
  47 #include "base/types.hh"
  48
  49 namespace X86ISA
  50 {
  51     //This really determines how many bytes are passed to the predecoder.
  52     typedef uint64_t MachInst;
  53
  54     enum Prefixes {
  55         NoOverride,
  56         ESOverride,
  57         CSOverride,
  58         SSOverride,
  59         DSOverride,
  60         FSOverride,
  61         GSOverride,
  62         RexPrefix,
  63         OperandSizeOverride,
  64         AddressSizeOverride,
  65         Lock,
  66         Rep,
  67         Repne
  68     };
  69
  70     BitUnion8(LegacyPrefixVector)
  71         Bitfield<7, 4> decodeVal;
  72         Bitfield<7> repne;
  73         Bitfield<6> rep;
  74         Bitfield<5> lock;
  75         Bitfield<4> op;
  76         Bitfield<3> addr;
  77         //There can be only one segment override, so they share the
  78         //first 3 bits in the legacyPrefixes bitfield.
  79         Bitfield<2,0> seg;
  80     EndBitUnion(LegacyPrefixVector)
  81
  82     BitUnion8(ModRM)
  83         Bitfield<7,6> mod;
  84         Bitfield<5,3> reg;
  85         Bitfield<2,0> rm;
  86     EndBitUnion(ModRM)
  87
  88     BitUnion8(Sib)
  89         Bitfield<7,6> scale;
  90         Bitfield<5,3> index;
  91         Bitfield<2,0> base;
  92     EndBitUnion(Sib)
  93
  94     BitUnion8(Rex)
  95         //This bit doesn't mean anything according to the ISA, but in
  96         //this implementation, it being set means an REX prefix was present.
  97         Bitfield<6> present;
  98         Bitfield<3> w;
  99         Bitfield<2> r;
 100         Bitfield<1> x;
 101         Bitfield<0> b;
 102     EndBitUnion(Rex)
 103
 104     BitUnion8(Opcode)
 105         Bitfield<7,3> top5;
 106         Bitfield<2,0> bottom3;
 107     EndBitUnion(Opcode)
 108
 109     BitUnion8(OperatingMode)
 110         Bitfield<3> mode;
 111         Bitfield<2,0> submode;
 112     EndBitUnion(OperatingMode)
 113
 114     enum X86Mode {
 115         LongMode,
 116         LegacyMode
 117     };
 118
 119     enum X86SubMode {
 120         SixtyFourBitMode,
 121         CompatabilityMode,
 122         ProtectedMode,
 123         Virtual8086Mode,
 124         RealMode
 125     };
 126
 127     //The intermediate structure the x86 predecoder returns.
 128     struct ExtMachInst
 129     {
 130         //Prefixes
 131         LegacyPrefixVector legacy;
 132         Rex rex;
 133         //This holds all of the bytes of the opcode
 134         struct
 135         {
 136             //The number of bytes in this opcode. Right now, we ignore that
 137             //this can be 3 in some cases
 138             uint8_t num;
 139             //The first byte detected in a 2+ byte opcode. Should be 0xF0.
 140             uint8_t prefixA;
 141             //The second byte detected in a 3+ byte opcode. Could be 0x38-0x3F
 142             //for some SSE instructions. 3dNow! instructions are handled as
 143             //two byte opcodes and then split out further by the immediate
 144             //byte.
 145             uint8_t prefixB;
 146             //The main opcode byte. The highest addressed byte in the opcode.
 147             Opcode op;
 148         } opcode;
 149         //Modifier bytes
 150         ModRM modRM;
 151         Sib sib;
 152         //Immediate fields
 153         uint64_t immediate;
 154         uint64_t displacement;
 155
 156         //The effective operand size.
 157         uint8_t opSize;
 158         //The effective address size.
 159         uint8_t addrSize;
 160         //The effective stack size.
 161         uint8_t stackSize;
 162         //The size of the displacement
 163         uint8_t dispSize;
 164
 165         //Mode information
 166         OperatingMode mode;
 167     };
 168
 169     inline static std::ostream &
 170         operator << (std::ostream & os, const ExtMachInst & emi)
 171     {
 172         ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
 173                      "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
 174                            "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
 175                      "modRM = %#x,\n\tsib = %#x,\n\t"
 176                      "immediate = %#x,\n\tdisplacement = %#x\n\t"
 177                      "dispSize = %d}\n",
 178                      (uint8_t)emi.legacy, (uint8_t)emi.rex,
 179                      emi.opcode.num, (uint8_t)emi.opcode.op,
 180                      emi.opcode.prefixA, emi.opcode.prefixB,
 181                      (uint8_t)emi.modRM, (uint8_t)emi.sib,
 182                      emi.immediate, emi.displacement, emi.dispSize);
 183         return os;
 184     }
 185
 186     inline static bool
 187         operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
 188     {
 189         if(emi1.legacy != emi2.legacy)
 190             return false;
 191         if(emi1.rex != emi2.rex)
 192             return false;
 193         if(emi1.opcode.num != emi2.opcode.num)
 194             return false;
 195         if(emi1.opcode.op != emi2.opcode.op)
 196             return false;
 197         if(emi1.opcode.prefixA != emi2.opcode.prefixA)
 198             return false;
 199         if(emi1.opcode.prefixB != emi2.opcode.prefixB)
 200             return false;
 201         if(emi1.modRM != emi2.modRM)
 202             return false;
 203         if(emi1.sib != emi2.sib)
 204             return false;
 205         if(emi1.immediate != emi2.immediate)
 206             return false;
 207         if(emi1.displacement != emi2.displacement)
 208             return false;
 209         if(emi1.mode != emi2.mode)
 210             return false;
 211         if(emi1.opSize != emi2.opSize)
 212             return false;
 213         if(emi1.addrSize != emi2.addrSize)
 214             return false;
 215         if(emi1.stackSize != emi2.stackSize)
 216             return false;
 217         if(emi1.dispSize != emi2.dispSize)
 218             return false;
 219         return true;
 220     }
 221
 222     struct CoreSpecific {
 223         int core_type;
 224     };
 225 };
 226
 227 #endif // __ARCH_X86_TYPES_HH__